2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __ASM_NIOS2_CACHE_H_
9 #define __ASM_NIOS2_CACHE_H_
12 * Valid L1 data cache line sizes for the NIOS2 architecture are 4,
13 * 16, and 32 bytes. We default to the largest of these values for
14 * alignment of DMA buffers.
16 #define ARCH_DMA_MINALIGN 32
18 #endif /* __ASM_NIOS2_CACHE_H_ */