2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __ASM_NIOS2_CACHE_H_
9 #define __ASM_NIOS2_CACHE_H_
11 extern void flush_dcache (unsigned long start, unsigned long size);
12 extern void flush_icache (unsigned long start, unsigned long size);
15 * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
16 * bytes. If the board configuration has not specified one we default to the
17 * largest of these values for alignment of DMA buffers.
19 #ifdef CONFIG_SYS_CACHELINE_SIZE
20 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
22 #define ARCH_DMA_MINALIGN 32
25 #endif /* __ASM_NIOS2_CACHE_H_ */