1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
4 * Scott McNutt <smcnutt@psyent.com>
7 #ifndef __ASM_NIOS2_CACHE_H_
8 #define __ASM_NIOS2_CACHE_H_
11 * Valid L1 data cache line sizes for the NIOS2 architecture are 4,
12 * 16, and 32 bytes. We default to the largest of these values for
13 * alignment of DMA buffers.
15 #define ARCH_DMA_MINALIGN 32
17 #endif /* __ASM_NIOS2_CACHE_H_ */