2 * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
3 * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
11 void flush_dcache_range(unsigned long addr, unsigned long stop)
13 ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
16 mtspr(SPR_DCBFR, addr);
21 void invalidate_dcache_range(unsigned long addr, unsigned long stop)
23 ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
26 mtspr(SPR_DCBIR, addr);
31 static void invalidate_icache_range(unsigned long addr, unsigned long stop)
33 ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;
36 mtspr(SPR_ICBIR, addr);
41 void flush_cache(unsigned long addr, unsigned long size)
43 flush_dcache_range(addr, addr + size);
44 invalidate_icache_range(addr, addr + size);
47 int icache_status(void)
49 return mfspr(SPR_SR) & SPR_SR_ICE;
55 unsigned long cache_set_size;
56 unsigned long cache_ways;
57 unsigned long cache_block_size;
59 iccfgr = mfspr(SPR_ICCFGR);
60 cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
61 cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
62 cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
64 return cache_set_size * cache_ways * cache_block_size;
67 int dcache_status(void)
69 return mfspr(SPR_SR) & SPR_SR_DCE;
75 unsigned long cache_set_size;
76 unsigned long cache_ways;
77 unsigned long cache_block_size;
79 dccfgr = mfspr(SPR_DCCFGR);
80 cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
81 cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
82 cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
84 return cache_set_size * cache_ways * cache_block_size;
87 void dcache_enable(void)
89 mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
90 asm volatile("l.nop");
91 asm volatile("l.nop");
92 asm volatile("l.nop");
93 asm volatile("l.nop");
94 asm volatile("l.nop");
95 asm volatile("l.nop");
96 asm volatile("l.nop");
97 asm volatile("l.nop");
100 void dcache_disable(void)
102 mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
105 void icache_enable(void)
107 mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
108 asm volatile("l.nop");
109 asm volatile("l.nop");
110 asm volatile("l.nop");
111 asm volatile("l.nop");
112 asm volatile("l.nop");
113 asm volatile("l.nop");
114 asm volatile("l.nop");
115 asm volatile("l.nop");
118 void icache_disable(void)
120 mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
125 if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
127 invalidate_icache_range(0, checkicache());
131 if (mfspr(SPR_UPR) & SPR_UPR_DCP) {
133 invalidate_dcache_range(0, checkdcache());