2 * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_OPENRISC_CACHE_H_
8 #define __ASM_OPENRISC_CACHE_H_
11 * Valid L1 data cache line sizes for the OpenRISC architecture are
13 * If the board configuration has not specified one we default to the
14 * largest of these values for alignment of DMA buffers.
16 #ifdef CONFIG_SYS_CACHELINE_SIZE
17 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
19 #define ARCH_DMA_MINALIGN 32
22 #endif /* __ASM_OPENRISC_CACHE_H_ */