2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* U-Boot - Startup Code for PowerPC based Embedded Boards
29 * The processor starts at 0xfff00100 and the code is executed
30 * from flash. The code is organized to be at an other address
31 * in memory, but as long we don't jump around before relocating.
32 * board_init lies at a quite high address and when the cpu has
33 * jumped there, everything is ok.
35 #include <asm-offsets.h>
40 #include <ppc_asm.tmpl>
43 #include <asm/cache.h>
45 #include <asm/u-boot.h>
47 #if !defined(CONFIG_DB64360) && \
48 !defined(CONFIG_DB64460) && \
49 !defined(CONFIG_CPCI750) && \
51 #include <galileo/gt64260R.h>
54 /* We don't want the MMU yet.
57 /* Machine Check and Recoverable Interr. */
58 #define MSR_KERNEL ( MSR_ME | MSR_RI )
61 * Set up GOT: Global Offset Table
63 * Use r12 to access the GOT
66 GOT_ENTRY(_GOT2_TABLE_)
67 GOT_ENTRY(_FIXUP_TABLE_)
70 GOT_ENTRY(_start_of_vectors)
71 GOT_ENTRY(_end_of_vectors)
72 GOT_ENTRY(transfer_to_handler)
75 GOT_ENTRY(__bss_end__)
76 GOT_ENTRY(__bss_start)
80 * r3 - 1st arg to board_init(): IMMP pointer
81 * r4 - 2nd arg to board_init(): boot flag
84 .long 0x27051956 /* U-Boot Magic Number */
87 .ascii U_BOOT_VERSION_STRING, "\0"
94 /* the boot code is located below the exception table */
96 .globl _start_of_vectors
100 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
102 /* Data Storage exception. "Never" generated on the 860. */
103 STD_EXCEPTION(0x300, DataStorage, UnknownException)
105 /* Instruction Storage exception. "Never" generated on the 860. */
106 STD_EXCEPTION(0x400, InstStorage, UnknownException)
108 /* External Interrupt exception. */
109 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
111 /* Alignment exception. */
114 EXCEPTION_PROLOG(SRR0, SRR1)
119 addi r3,r1,STACK_FRAME_OVERHEAD
120 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
122 /* Program check exception */
125 EXCEPTION_PROLOG(SRR0, SRR1)
126 addi r3,r1,STACK_FRAME_OVERHEAD
127 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
130 /* No FPU on MPC8xx. This exception is not supposed to happen.
132 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
134 /* I guess we could implement decrementer, and may have
135 * to someday for timekeeping.
137 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
138 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
139 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
140 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
141 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
143 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
144 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
147 * On the MPC8xx, this is a software emulation interrupt. It
148 * occurs for all unimplemented and illegal instructions.
150 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
152 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
153 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
154 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
155 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
157 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
158 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
159 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
160 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
161 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
162 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
163 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
165 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
166 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
167 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
168 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
170 .globl _end_of_vectors
176 /* disable everything */
185 /* init the L2 cache */
186 addis r3, r0, L2_INIT@h
187 ori r3, r3, L2_INIT@l
191 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
194 * dssall instruction, gas doesn't have it yet
195 * ...for altivec, data stream stop all this probably
196 * isn't needed unless we warm (software) reboot U-Boot
201 /* invalidate the L2 cache */
202 bl l2cache_invalidate
205 #ifdef CONFIG_SYS_BOARD_ASM_INIT
211 * Calculate absolute address in FLASH and jump there
212 *------------------------------------------------------*/
213 lis r3, CONFIG_SYS_MONITOR_BASE@h
214 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
215 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
220 /* let the C-code set up the rest */
222 /* Be careful to keep code relocatable ! */
223 /*------------------------------------------------------*/
225 /* perform low-level init */
226 /* sdram init, galileo init, etc */
227 /* r3: NHR bit from HID0 */
234 * Cache must be enabled here for stack-in-cache trick.
235 * This means we need to enable the BATS.
237 * 1) for the EVB, original gt regs need to be mapped
238 * 2) need to have an IBAT for the 0xf region,
239 * we are running there!
240 * Cache should be turned on after BATs, since by default
241 * everything is write-through.
242 * The init-mem BAT can be reused after reloc. The old
243 * gt-regs BAT can be reused after board_init_f calls
244 * board_early_init_f (EVB only).
246 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
247 /* enable address translation */
251 /* enable and invalidate the data cache */
255 #ifdef CONFIG_SYS_INIT_RAM_LOCK
260 /* set up the stack pointer in our newly created
262 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
263 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
265 li r0, 0 /* Make room for stack frame header and */
266 stwu r0, -4(r1) /* clear final stack frame so that */
267 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
269 GET_GOT /* initialize GOT access */
271 /* run low-level CPU init code (from Flash) */
275 /* run 1st part of board init code (from Flash) */
279 /* NOTREACHED - board_init_f() does not return */
281 .globl invalidate_bats
283 /* invalidate BATs */
288 #ifdef CONFIG_HIGH_BATS
299 #ifdef CONFIG_HIGH_BATS
309 /* setup_bats - set them up to some initial state */
315 addis r4, r0, CONFIG_SYS_IBAT0L@h
316 ori r4, r4, CONFIG_SYS_IBAT0L@l
317 addis r3, r0, CONFIG_SYS_IBAT0U@h
318 ori r3, r3, CONFIG_SYS_IBAT0U@l
324 addis r4, r0, CONFIG_SYS_DBAT0L@h
325 ori r4, r4, CONFIG_SYS_DBAT0L@l
326 addis r3, r0, CONFIG_SYS_DBAT0U@h
327 ori r3, r3, CONFIG_SYS_DBAT0U@l
333 addis r4, r0, CONFIG_SYS_IBAT1L@h
334 ori r4, r4, CONFIG_SYS_IBAT1L@l
335 addis r3, r0, CONFIG_SYS_IBAT1U@h
336 ori r3, r3, CONFIG_SYS_IBAT1U@l
342 addis r4, r0, CONFIG_SYS_DBAT1L@h
343 ori r4, r4, CONFIG_SYS_DBAT1L@l
344 addis r3, r0, CONFIG_SYS_DBAT1U@h
345 ori r3, r3, CONFIG_SYS_DBAT1U@l
351 addis r4, r0, CONFIG_SYS_IBAT2L@h
352 ori r4, r4, CONFIG_SYS_IBAT2L@l
353 addis r3, r0, CONFIG_SYS_IBAT2U@h
354 ori r3, r3, CONFIG_SYS_IBAT2U@l
360 addis r4, r0, CONFIG_SYS_DBAT2L@h
361 ori r4, r4, CONFIG_SYS_DBAT2L@l
362 addis r3, r0, CONFIG_SYS_DBAT2U@h
363 ori r3, r3, CONFIG_SYS_DBAT2U@l
369 addis r4, r0, CONFIG_SYS_IBAT3L@h
370 ori r4, r4, CONFIG_SYS_IBAT3L@l
371 addis r3, r0, CONFIG_SYS_IBAT3U@h
372 ori r3, r3, CONFIG_SYS_IBAT3U@l
378 addis r4, r0, CONFIG_SYS_DBAT3L@h
379 ori r4, r4, CONFIG_SYS_DBAT3L@l
380 addis r3, r0, CONFIG_SYS_DBAT3U@h
381 ori r3, r3, CONFIG_SYS_DBAT3U@l
386 #ifdef CONFIG_HIGH_BATS
388 addis r4, r0, CONFIG_SYS_IBAT4L@h
389 ori r4, r4, CONFIG_SYS_IBAT4L@l
390 addis r3, r0, CONFIG_SYS_IBAT4U@h
391 ori r3, r3, CONFIG_SYS_IBAT4U@l
397 addis r4, r0, CONFIG_SYS_DBAT4L@h
398 ori r4, r4, CONFIG_SYS_DBAT4L@l
399 addis r3, r0, CONFIG_SYS_DBAT4U@h
400 ori r3, r3, CONFIG_SYS_DBAT4U@l
406 addis r4, r0, CONFIG_SYS_IBAT5L@h
407 ori r4, r4, CONFIG_SYS_IBAT5L@l
408 addis r3, r0, CONFIG_SYS_IBAT5U@h
409 ori r3, r3, CONFIG_SYS_IBAT5U@l
415 addis r4, r0, CONFIG_SYS_DBAT5L@h
416 ori r4, r4, CONFIG_SYS_DBAT5L@l
417 addis r3, r0, CONFIG_SYS_DBAT5U@h
418 ori r3, r3, CONFIG_SYS_DBAT5U@l
424 addis r4, r0, CONFIG_SYS_IBAT6L@h
425 ori r4, r4, CONFIG_SYS_IBAT6L@l
426 addis r3, r0, CONFIG_SYS_IBAT6U@h
427 ori r3, r3, CONFIG_SYS_IBAT6U@l
433 addis r4, r0, CONFIG_SYS_DBAT6L@h
434 ori r4, r4, CONFIG_SYS_DBAT6L@l
435 addis r3, r0, CONFIG_SYS_DBAT6U@h
436 ori r3, r3, CONFIG_SYS_DBAT6U@l
442 addis r4, r0, CONFIG_SYS_IBAT7L@h
443 ori r4, r4, CONFIG_SYS_IBAT7L@l
444 addis r3, r0, CONFIG_SYS_IBAT7U@h
445 ori r3, r3, CONFIG_SYS_IBAT7U@l
451 addis r4, r0, CONFIG_SYS_DBAT7L@h
452 ori r4, r4, CONFIG_SYS_DBAT7L@l
453 addis r3, r0, CONFIG_SYS_DBAT7U@h
454 ori r3, r3, CONFIG_SYS_DBAT7U@l
460 /* bats are done, now invalidate the TLBs */
463 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
476 .globl enable_addr_trans
478 /* enable address translation */
480 ori r5, r5, (MSR_IR | MSR_DR)
485 .globl disable_addr_trans
487 /* disable address translation */
490 andi. r0, r3, (MSR_IR | MSR_DR)
498 * This code finishes saving the registers to the exception frame
499 * and jumps to the appropriate handler for the exception.
500 * Register r21 is pointer into trap frame, r1 has new stack pointer.
502 .globl transfer_to_handler
513 andi. r24,r23,0x3f00 /* get vector offset */
517 mtspr SPRG2,r22 /* r1 is now kernel sp */
518 lwz r24,0(r23) /* virtual address of handler */
519 lwz r23,4(r23) /* where to go when done */
524 rfi /* jump to handler, enable MMU */
527 mfmsr r28 /* Disable interrupts */
531 SYNC /* Some chip revs need this... */
546 lwz r2,_NIP(r1) /* Restore environment */
565 /*-----------------------------------------------------------------------*/
567 * void relocate_code (addr_sp, gd, addr_moni)
569 * This "function" does not return, instead it continues in RAM
570 * after relocating the monitor code.
574 * r5 = length in bytes
579 mr r1, r3 /* Set new stack pointer */
580 mr r9, r4 /* Save copy of Global Data pointer */
581 mr r10, r5 /* Save copy of Destination Address */
584 mr r3, r5 /* Destination Address */
585 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
586 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
587 lwz r5, GOT(__init_end)
589 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
594 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
600 /* First our own GOT */
602 /* then the one used by the C code */
609 bl board_relocate_rom
611 mr r3, r10 /* Destination Address */
612 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
613 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
614 lwz r5, GOT(__init_end)
616 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
621 beq cr1,4f /* In place copy is not necessary */
622 beq 7f /* Protect against 0 count */
641 * Now flush the cache: note that we must start from a cache aligned
642 * address. Otherwise we might miss one cache line.
646 beq 7f /* Always flush prefetch queue in any case */
654 sync /* Wait for all dcbst to complete on bus */
660 7: sync /* Wait for all icbi to complete on bus */
664 * We are done. Do not return, instead branch to second part of board
665 * initialization, now running from RAM.
667 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
676 * Relocation Function, r12 point to got2+0x8000
678 * Adjust got2 pointers, no need to check for 0, this code
679 * already puts a few entries in the table.
681 li r0,__got2_entries@sectoff@l
682 la r3,GOT(_GOT2_TABLE_)
683 lwz r11,GOT(_GOT2_TABLE_)
695 * Now adjust the fixups and the pointers to the fixups
696 * in case we need to move ourselves again.
698 li r0,__fixup_entries@sectoff@l
699 lwz r3,GOT(_FIXUP_TABLE_)
715 * Now clear BSS segment
717 lwz r3,GOT(__bss_start)
718 lwz r4,GOT(__bss_end__)
730 mr r3, r10 /* Destination Address */
731 #if defined(CONFIG_DB64360) || \
732 defined(CONFIG_DB64460) || \
733 defined(CONFIG_CPCI750) || \
734 defined(CONFIG_PPMC7XX) || \
736 mr r4, r9 /* Use RAM copy of the global data */
740 /* not reached - end relocate_code */
741 /*-----------------------------------------------------------------------*/
744 * Copy exception vector code to low memory
747 * r7: source address, r8: end address, r9: target address
751 mflr r4 /* save link register */
754 lwz r8, GOT(_end_of_vectors)
756 li r9, 0x100 /* reset vector always at 0x100 */
759 bgelr /* return if r7>=r8 - just in case */
769 * relocate `hdlr' and `int_return' entries
771 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
772 li r8, Alignment - _start + EXC_OFF_SYS_RESET
775 addi r7, r7, 0x100 /* next exception vector */
779 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
782 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
785 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
786 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
789 addi r7, r7, 0x100 /* next exception vector */
793 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
794 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
797 addi r7, r7, 0x100 /* next exception vector */
801 /* enable execptions from RAM vectors */
807 mtlr r4 /* restore link register */
810 #ifdef CONFIG_SYS_INIT_RAM_LOCK
812 /* Allocate Initial RAM in data cache.
814 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
815 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
816 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
817 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
824 /* Lock the data cache */
832 .globl unlock_ram_in_cache
834 /* invalidate the INIT_RAM section */
835 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
836 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
837 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
838 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
843 sync /* Wait for all icbi to complete on bus */
846 /* Unlock the data cache and invalidate it */