2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 /* U-Boot - Startup Code for PowerPC based Embedded Boards
13 * The processor starts at 0xfff00100 and the code is executed
14 * from flash. The code is organized to be at an other address
15 * in memory, but as long we don't jump around before relocating.
16 * board_init lies at a quite high address and when the cpu has
17 * jumped there, everything is ok.
19 #include <asm-offsets.h>
24 #include <ppc_asm.tmpl>
27 #include <asm/cache.h>
29 #include <asm/u-boot.h>
31 /* We don't want the MMU yet.
34 /* Machine Check and Recoverable Interr. */
35 #define MSR_KERNEL ( MSR_ME | MSR_RI )
38 * Set up GOT: Global Offset Table
40 * Use r12 to access the GOT
43 GOT_ENTRY(_GOT2_TABLE_)
44 GOT_ENTRY(_FIXUP_TABLE_)
47 GOT_ENTRY(_start_of_vectors)
48 GOT_ENTRY(_end_of_vectors)
49 GOT_ENTRY(transfer_to_handler)
53 GOT_ENTRY(__bss_start)
57 * r3 - 1st arg to board_init(): IMMP pointer
58 * r4 - 2nd arg to board_init(): boot flag
61 .long 0x27051956 /* U-Boot Magic Number */
64 .ascii U_BOOT_VERSION_STRING, "\0"
71 /* the boot code is located below the exception table */
73 .globl _start_of_vectors
77 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
79 /* Data Storage exception. "Never" generated on the 860. */
80 STD_EXCEPTION(0x300, DataStorage, UnknownException)
82 /* Instruction Storage exception. "Never" generated on the 860. */
83 STD_EXCEPTION(0x400, InstStorage, UnknownException)
85 /* External Interrupt exception. */
86 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
88 /* Alignment exception. */
91 EXCEPTION_PROLOG(SRR0, SRR1)
96 addi r3,r1,STACK_FRAME_OVERHEAD
97 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
99 /* Program check exception */
102 EXCEPTION_PROLOG(SRR0, SRR1)
103 addi r3,r1,STACK_FRAME_OVERHEAD
104 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
107 /* No FPU on MPC8xx. This exception is not supposed to happen.
109 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
111 /* I guess we could implement decrementer, and may have
112 * to someday for timekeeping.
114 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
115 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
116 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
117 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
118 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
120 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
121 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
124 * On the MPC8xx, this is a software emulation interrupt. It
125 * occurs for all unimplemented and illegal instructions.
127 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
129 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
130 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
131 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
132 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
134 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
135 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
136 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
137 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
138 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
139 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
140 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
142 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
143 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
144 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
145 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
147 .globl _end_of_vectors
153 /* disable everything */
162 /* init the L2 cache */
163 addis r3, r0, L2_INIT@h
164 ori r3, r3, L2_INIT@l
168 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
171 * dssall instruction, gas doesn't have it yet
172 * ...for altivec, data stream stop all this probably
173 * isn't needed unless we warm (software) reboot U-Boot
178 /* invalidate the L2 cache */
179 bl l2cache_invalidate
182 #ifdef CONFIG_SYS_BOARD_ASM_INIT
188 * Calculate absolute address in FLASH and jump there
189 *------------------------------------------------------*/
190 lis r3, CONFIG_SYS_MONITOR_BASE@h
191 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
192 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
197 /* let the C-code set up the rest */
199 /* Be careful to keep code relocatable ! */
200 /*------------------------------------------------------*/
202 /* perform low-level init */
203 /* sdram init, galileo init, etc */
204 /* r3: NHR bit from HID0 */
211 * Cache must be enabled here for stack-in-cache trick.
212 * This means we need to enable the BATS.
214 * 1) for the EVB, original gt regs need to be mapped
215 * 2) need to have an IBAT for the 0xf region,
216 * we are running there!
217 * Cache should be turned on after BATs, since by default
218 * everything is write-through.
219 * The init-mem BAT can be reused after reloc. The old
220 * gt-regs BAT can be reused after board_init_f calls
221 * board_early_init_f (EVB only).
223 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
224 /* enable address translation */
228 /* enable and invalidate the data cache */
232 #ifdef CONFIG_SYS_INIT_RAM_LOCK
237 /* set up the stack pointer in our newly created
239 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
240 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
242 li r0, 0 /* Make room for stack frame header and */
243 stwu r0, -4(r1) /* clear final stack frame so that */
244 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
246 GET_GOT /* initialize GOT access */
248 /* run low-level CPU init code (from Flash) */
252 /* run 1st part of board init code (from Flash) */
256 /* NOTREACHED - board_init_f() does not return */
258 .globl invalidate_bats
260 /* invalidate BATs */
265 #ifdef CONFIG_HIGH_BATS
276 #ifdef CONFIG_HIGH_BATS
286 /* setup_bats - set them up to some initial state */
292 addis r4, r0, CONFIG_SYS_IBAT0L@h
293 ori r4, r4, CONFIG_SYS_IBAT0L@l
294 addis r3, r0, CONFIG_SYS_IBAT0U@h
295 ori r3, r3, CONFIG_SYS_IBAT0U@l
301 addis r4, r0, CONFIG_SYS_DBAT0L@h
302 ori r4, r4, CONFIG_SYS_DBAT0L@l
303 addis r3, r0, CONFIG_SYS_DBAT0U@h
304 ori r3, r3, CONFIG_SYS_DBAT0U@l
310 addis r4, r0, CONFIG_SYS_IBAT1L@h
311 ori r4, r4, CONFIG_SYS_IBAT1L@l
312 addis r3, r0, CONFIG_SYS_IBAT1U@h
313 ori r3, r3, CONFIG_SYS_IBAT1U@l
319 addis r4, r0, CONFIG_SYS_DBAT1L@h
320 ori r4, r4, CONFIG_SYS_DBAT1L@l
321 addis r3, r0, CONFIG_SYS_DBAT1U@h
322 ori r3, r3, CONFIG_SYS_DBAT1U@l
328 addis r4, r0, CONFIG_SYS_IBAT2L@h
329 ori r4, r4, CONFIG_SYS_IBAT2L@l
330 addis r3, r0, CONFIG_SYS_IBAT2U@h
331 ori r3, r3, CONFIG_SYS_IBAT2U@l
337 addis r4, r0, CONFIG_SYS_DBAT2L@h
338 ori r4, r4, CONFIG_SYS_DBAT2L@l
339 addis r3, r0, CONFIG_SYS_DBAT2U@h
340 ori r3, r3, CONFIG_SYS_DBAT2U@l
346 addis r4, r0, CONFIG_SYS_IBAT3L@h
347 ori r4, r4, CONFIG_SYS_IBAT3L@l
348 addis r3, r0, CONFIG_SYS_IBAT3U@h
349 ori r3, r3, CONFIG_SYS_IBAT3U@l
355 addis r4, r0, CONFIG_SYS_DBAT3L@h
356 ori r4, r4, CONFIG_SYS_DBAT3L@l
357 addis r3, r0, CONFIG_SYS_DBAT3U@h
358 ori r3, r3, CONFIG_SYS_DBAT3U@l
363 #ifdef CONFIG_HIGH_BATS
365 addis r4, r0, CONFIG_SYS_IBAT4L@h
366 ori r4, r4, CONFIG_SYS_IBAT4L@l
367 addis r3, r0, CONFIG_SYS_IBAT4U@h
368 ori r3, r3, CONFIG_SYS_IBAT4U@l
374 addis r4, r0, CONFIG_SYS_DBAT4L@h
375 ori r4, r4, CONFIG_SYS_DBAT4L@l
376 addis r3, r0, CONFIG_SYS_DBAT4U@h
377 ori r3, r3, CONFIG_SYS_DBAT4U@l
383 addis r4, r0, CONFIG_SYS_IBAT5L@h
384 ori r4, r4, CONFIG_SYS_IBAT5L@l
385 addis r3, r0, CONFIG_SYS_IBAT5U@h
386 ori r3, r3, CONFIG_SYS_IBAT5U@l
392 addis r4, r0, CONFIG_SYS_DBAT5L@h
393 ori r4, r4, CONFIG_SYS_DBAT5L@l
394 addis r3, r0, CONFIG_SYS_DBAT5U@h
395 ori r3, r3, CONFIG_SYS_DBAT5U@l
401 addis r4, r0, CONFIG_SYS_IBAT6L@h
402 ori r4, r4, CONFIG_SYS_IBAT6L@l
403 addis r3, r0, CONFIG_SYS_IBAT6U@h
404 ori r3, r3, CONFIG_SYS_IBAT6U@l
410 addis r4, r0, CONFIG_SYS_DBAT6L@h
411 ori r4, r4, CONFIG_SYS_DBAT6L@l
412 addis r3, r0, CONFIG_SYS_DBAT6U@h
413 ori r3, r3, CONFIG_SYS_DBAT6U@l
419 addis r4, r0, CONFIG_SYS_IBAT7L@h
420 ori r4, r4, CONFIG_SYS_IBAT7L@l
421 addis r3, r0, CONFIG_SYS_IBAT7U@h
422 ori r3, r3, CONFIG_SYS_IBAT7U@l
428 addis r4, r0, CONFIG_SYS_DBAT7L@h
429 ori r4, r4, CONFIG_SYS_DBAT7L@l
430 addis r3, r0, CONFIG_SYS_DBAT7U@h
431 ori r3, r3, CONFIG_SYS_DBAT7U@l
437 /* bats are done, now invalidate the TLBs */
440 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
453 .globl enable_addr_trans
455 /* enable address translation */
457 ori r5, r5, (MSR_IR | MSR_DR)
462 .globl disable_addr_trans
464 /* disable address translation */
467 andi. r0, r3, (MSR_IR | MSR_DR)
475 * This code finishes saving the registers to the exception frame
476 * and jumps to the appropriate handler for the exception.
477 * Register r21 is pointer into trap frame, r1 has new stack pointer.
479 .globl transfer_to_handler
490 andi. r24,r23,0x3f00 /* get vector offset */
494 mtspr SPRG2,r22 /* r1 is now kernel sp */
495 lwz r24,0(r23) /* virtual address of handler */
496 lwz r23,4(r23) /* where to go when done */
501 rfi /* jump to handler, enable MMU */
504 mfmsr r28 /* Disable interrupts */
508 SYNC /* Some chip revs need this... */
523 lwz r2,_NIP(r1) /* Restore environment */
542 /*-----------------------------------------------------------------------*/
544 * void relocate_code (addr_sp, gd, addr_moni)
546 * This "function" does not return, instead it continues in RAM
547 * after relocating the monitor code.
551 * r5 = length in bytes
556 mr r1, r3 /* Set new stack pointer */
557 mr r9, r4 /* Save copy of Global Data pointer */
558 mr r10, r5 /* Save copy of Destination Address */
561 mr r3, r5 /* Destination Address */
562 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
563 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
564 lwz r5, GOT(__init_end)
566 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
571 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
577 /* First our own GOT */
579 /* then the one used by the C code */
586 bl board_relocate_rom
588 mr r3, r10 /* Destination Address */
589 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
590 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
591 lwz r5, GOT(__init_end)
593 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
598 beq cr1,4f /* In place copy is not necessary */
599 beq 7f /* Protect against 0 count */
618 * Now flush the cache: note that we must start from a cache aligned
619 * address. Otherwise we might miss one cache line.
623 beq 7f /* Always flush prefetch queue in any case */
631 sync /* Wait for all dcbst to complete on bus */
637 7: sync /* Wait for all icbi to complete on bus */
641 * We are done. Do not return, instead branch to second part of board
642 * initialization, now running from RAM.
644 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
653 * Relocation Function, r12 point to got2+0x8000
655 * Adjust got2 pointers, no need to check for 0, this code
656 * already puts a few entries in the table.
658 li r0,__got2_entries@sectoff@l
659 la r3,GOT(_GOT2_TABLE_)
660 lwz r11,GOT(_GOT2_TABLE_)
672 * Now adjust the fixups and the pointers to the fixups
673 * in case we need to move ourselves again.
675 li r0,__fixup_entries@sectoff@l
676 lwz r3,GOT(_FIXUP_TABLE_)
692 * Now clear BSS segment
694 lwz r3,GOT(__bss_start)
695 lwz r4,GOT(__bss_end)
707 mr r3, r10 /* Destination Address */
708 #if defined(CONFIG_PPMC7XX)
709 mr r4, r9 /* Use RAM copy of the global data */
713 /* not reached - end relocate_code */
714 /*-----------------------------------------------------------------------*/
717 * Copy exception vector code to low memory
720 * r7: source address, r8: end address, r9: target address
724 mflr r4 /* save link register */
727 lwz r8, GOT(_end_of_vectors)
729 li r9, 0x100 /* reset vector always at 0x100 */
732 bgelr /* return if r7>=r8 - just in case */
742 * relocate `hdlr' and `int_return' entries
744 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
745 li r8, Alignment - _start + EXC_OFF_SYS_RESET
748 addi r7, r7, 0x100 /* next exception vector */
752 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
755 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
758 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
759 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
762 addi r7, r7, 0x100 /* next exception vector */
766 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
767 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
770 addi r7, r7, 0x100 /* next exception vector */
774 /* enable execptions from RAM vectors */
780 mtlr r4 /* restore link register */
783 #ifdef CONFIG_SYS_INIT_RAM_LOCK
785 /* Allocate Initial RAM in data cache.
787 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
788 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
789 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
790 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
797 /* Lock the data cache */
805 .globl unlock_ram_in_cache
807 /* invalidate the INIT_RAM section */
808 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
809 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
810 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
811 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
816 sync /* Wait for all icbi to complete on bus */
819 /* Unlock the data cache and invalidate it */