2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
3 * Copyright (C) 2007-2009 DENX Software Engineering
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Derived from the MPC83xx code.
29 #include <asm/mpc512x.h>
30 #include <asm/processor.h>
32 DECLARE_GLOBAL_DATA_PTR;
35 * Set up the memory map, initialize registers,
37 void cpu_init_f (volatile immap_t * im)
41 /* Pointer is writable since we allocated a register for it */
42 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
44 /* Clear initial global data */
45 memset ((void *) gd, 0, sizeof (gd_t));
47 /* Local Window and chip select configuration */
48 #if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
49 out_be32(&im->sysconf.lpcs0aw,
50 CSAW_START(CONFIG_SYS_CS0_START) |
51 CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE));
52 sync_law(&im->sysconf.lpcs0aw);
54 #if defined(CONFIG_SYS_CS0_CFG)
55 out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
58 #if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
59 out_be32(&im->sysconf.lpcs1aw,
60 CSAW_START(CONFIG_SYS_CS1_START) |
61 CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE));
62 sync_law(&im->sysconf.lpcs1aw);
64 #if defined(CONFIG_SYS_CS1_CFG)
65 out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
68 #if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE)
69 out_be32(&im->sysconf.lpcs2aw,
70 CSAW_START(CONFIG_SYS_CS2_START) |
71 CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE));
72 sync_law(&im->sysconf.lpcs2aw);
74 #if defined(CONFIG_SYS_CS2_CFG)
75 out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
78 #if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
79 out_be32(&im->sysconf.lpcs3aw,
80 CSAW_START(CONFIG_SYS_CS3_START) |
81 CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE));
82 sync_law(&im->sysconf.lpcs3aw);
84 #if defined(CONFIG_SYS_CS3_CFG)
85 out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG);
88 #if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
89 out_be32(&im->sysconf.lpcs4aw,
90 CSAW_START(CONFIG_SYS_CS4_START) |
91 CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE));
92 sync_law(&im->sysconf.lpcs4aw);
94 #if defined(CONFIG_SYS_CS4_CFG)
95 out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG);
98 #if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
99 out_be32(&im->sysconf.lpcs5aw,
100 CSAW_START(CONFIG_SYS_CS5_START) |
101 CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE));
102 sync_law(&im->sysconf.lpcs5aw);
104 #if defined(CONFIG_SYS_CS5_CFG)
105 out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG);
108 #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
109 out_be32(&im->sysconf.lpcs6aw,
110 CSAW_START(CONFIG_SYS_CS6_START) |
111 CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE));
112 sync_law(&im->sysconf.lpcs6aw);
114 #if defined(CONFIG_SYS_CS6_CFG)
115 out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
118 #if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
119 out_be32(&im->sysconf.lpcs7aw,
120 CSAW_START(CONFIG_SYS_CS7_START) |
121 CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE));
122 sync_law(&im->sysconf.lpcs7aw);
124 #if defined(CONFIG_SYS_CS7_CFG)
125 out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG);
128 #if defined CONFIG_SYS_CS_ALETIMING
129 if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2)
130 out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
132 #if defined CONFIG_SYS_CS_BURST
133 out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST);
135 #if defined CONFIG_SYS_CS_DEADCYCLE
136 out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE);
138 #if defined CONFIG_SYS_CS_HOLDCYCLE
139 out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE);
142 /* system performance tweaking */
144 #ifdef CONFIG_SYS_ACR_PIPE_DEP
145 /* Arbiter pipeline depth */
146 out_be32(&im->arbiter.acr,
147 (im->arbiter.acr & ~ACR_PIPE_DEP) |
148 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
152 #ifdef CONFIG_SYS_ACR_RPTCNT
153 /* Arbiter repeat count */
154 out_be32(im->arbiter.acr,
155 (im->arbiter.acr & ~(ACR_RPTCNT)) |
156 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
160 /* RSR - Reset Status Register - clear all status */
161 gd->arch.reset_status = im->reset.rsr;
162 out_be32(&im->reset.rsr, ~RSR_RES);
165 * RMR - Reset Mode Register - enable checkstop reset
167 out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
169 /* Set IPS-CSB divider: IPS = 1/2 CSB */
170 ips_div = in_be32(&im->clk.scfr[0]);
171 ips_div &= ~(SCFR1_IPS_DIV_MASK);
172 ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
173 out_be32(&im->clk.scfr[0], ips_div);
176 clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
177 SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
181 clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
182 SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
186 clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
187 SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
191 * Enable Time Base/Decrementer
193 * NOTICE: TB needs to be enabled as early as possible in order to
194 * have udelay() working; if not enabled, usually leads to a hang, like
195 * during FLASH chip identification etc.
197 setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
202 out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
203 out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
204 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
205 setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
209 int cpu_init_r (void)