2 * (C) Copyright 2000-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 DECLARE_GLOBAL_DATA_PTR;
16 * Breath some life into the CPU...
18 * Set up the memory map,
19 * initialize a bunch of registers.
21 void cpu_init_f (void)
23 volatile struct mpc5xxx_mmap_ctl *mm =
24 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
25 volatile struct mpc5xxx_lpb *lpb =
26 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
27 volatile struct mpc5xxx_gpio *gpio =
28 (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
29 volatile struct mpc5xxx_xlb *xlb =
30 (struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
31 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
32 volatile struct mpc5xxx_cdm *cdm =
33 (struct mpc5xxx_cdm *) MPC5XXX_CDM;
34 #endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
35 #if defined(CONFIG_WATCHDOG)
36 volatile struct mpc5xxx_gpt *gpt0 =
37 (struct mpc5xxx_gpt *) MPC5XXX_GPT;
38 #endif /* CONFIG_WATCHDOG */
39 unsigned long addecr = (1 << 25); /* Boot_CS */
40 /* Pointer is writable since we allocated a register for it */
41 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
43 /* Clear initial global data */
44 memset ((void *) gd, 0, sizeof (gd_t));
47 * Memory Controller: configure chip selects and enable them
49 #if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
50 out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
51 out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
52 CONFIG_SYS_BOOTCS_SIZE));
54 #if defined(CONFIG_SYS_BOOTCS_CFG)
55 out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
58 #if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
59 out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
60 out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
61 CONFIG_SYS_CS0_SIZE));
62 /* CS0 and BOOT_CS cannot be enabled at once. */
63 /* addecr |= (1 << 16); */
65 #if defined(CONFIG_SYS_CS0_CFG)
66 out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
69 #if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
70 out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
71 out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
72 CONFIG_SYS_CS1_SIZE));
75 #if defined(CONFIG_SYS_CS1_CFG)
76 out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
79 #if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
80 out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
81 out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
82 CONFIG_SYS_CS2_SIZE));
85 #if defined(CONFIG_SYS_CS2_CFG)
86 out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
89 #if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
90 out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
91 out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
92 CONFIG_SYS_CS3_SIZE));
95 #if defined(CONFIG_SYS_CS3_CFG)
96 out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
99 #if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
100 out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
101 out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
102 CONFIG_SYS_CS4_SIZE));
105 #if defined(CONFIG_SYS_CS4_CFG)
106 out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
109 #if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
110 out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
111 out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
112 CONFIG_SYS_CS5_SIZE));
115 #if defined(CONFIG_SYS_CS5_CFG)
116 out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
120 #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
121 out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
122 out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
123 CONFIG_SYS_CS6_SIZE));
126 #if defined(CONFIG_SYS_CS6_CFG)
127 out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
130 #if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
131 out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
132 out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
133 CONFIG_SYS_CS7_SIZE));
136 #if defined(CONFIG_SYS_CS7_CFG)
137 out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
140 #if defined(CONFIG_SYS_CS_BURST)
141 out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
143 #if defined(CONFIG_SYS_CS_DEADCYCLE)
144 out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
147 /* Enable chip selects */
148 out_be32(&mm->ipbi_ws_ctrl, addecr);
149 out_be32(&lpb->cs_ctrl, (1 << 24));
151 /* Setup pin multiplexing */
152 #if defined(CONFIG_SYS_GPS_PORT_CONFIG)
153 out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
157 #if defined(CONFIG_SYS_GPIO_DATADIR)
158 out_be32(&gpio->simple_ddr, CONFIG_SYS_GPIO_DATADIR);
160 #if defined(CONFIG_SYS_GPIO_OPENDRAIN)
161 out_be32(&gpio->simple_ode, CONFIG_SYS_GPIO_OPENDRAIN);
163 #if defined(CONFIG_SYS_GPIO_DATAVALUE)
164 out_be32(&gpio->simple_dvo, CONFIG_SYS_GPIO_DATAVALUE);
166 #if defined(CONFIG_SYS_GPIO_ENABLE)
167 out_be32(&gpio->simple_gpioe, CONFIG_SYS_GPIO_ENABLE);
170 /* enable timebase */
171 setbits_be32(&xlb->config, (1 << 13));
173 /* Enable snooping for RAM */
174 setbits_be32(&xlb->config, (1 << 15));
175 out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
177 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
178 /* Motorola reports IPB should better run at 133 MHz. */
179 setbits_be32(&mm->ipbi_ws_ctrl, 1);
180 /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
181 addecr = in_be32(&cdm->cfg);
183 # if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
184 /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
187 /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
189 # endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
190 out_be32(&cdm->cfg, addecr);
191 #endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
192 /* Configure the XLB Arbiter */
193 out_be32(&xlb->master_pri_enable, 0xff);
194 out_be32(&xlb->master_priority, 0x11111111);
196 #if defined(CONFIG_SYS_XLB_PIPELINING)
197 /* Enable piplining */
198 clrbits_be32(&xlb->config, (1 << 31));
201 #if defined(CONFIG_WATCHDOG)
202 /* Charge the watchdog timer - prescaler = 64k, count = 64k*/
203 out_be32(&gpt0->cir, 0x0000ffff);
204 out_be32(&gpt0->emsr, 0x9004); /* wden|ce|timer_ms */
206 reset_5xxx_watchdog();
207 #endif /* CONFIG_WATCHDOG */
211 * initialize higher level parts of CPU like time base and timers
213 int cpu_init_r (void)
215 volatile struct mpc5xxx_intr *intr =
216 (struct mpc5xxx_intr *) MPC5XXX_ICTL;
218 /* mask all interrupts */
219 out_be32(&intr->per_mask, 0xffffff00);
220 setbits_be32(&intr->main_mask, 0x0001ffff);
221 clrbits_be32(&intr->ctrl, 0x00000f00);
222 /* route critical ints to normal ints */
223 setbits_be32(&intr->ctrl, 0x00000001);
225 #if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
226 /* load FEC microcode */