2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 * U-Boot - Startup Code for MPC5xxx CPUs
12 #include <asm-offsets.h>
17 #define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */
19 #include <ppc_asm.tmpl>
22 #include <asm/cache.h>
24 #include <asm/u-boot.h>
26 /* We don't want the MMU yet.
29 /* Floating Point enable, Machine Check and Recoverable Interr. */
31 #define MSR_KERNEL (MSR_FP|MSR_RI)
33 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
36 #ifndef CONFIG_SPL_BUILD
38 * Set up GOT: Global Offset Table
40 * Use r12 to access the GOT
43 GOT_ENTRY(_GOT2_TABLE_)
44 GOT_ENTRY(_FIXUP_TABLE_)
47 GOT_ENTRY(_start_of_vectors)
48 GOT_ENTRY(_end_of_vectors)
49 GOT_ENTRY(transfer_to_handler)
53 GOT_ENTRY(__bss_start)
63 .ascii U_BOOT_VERSION_STRING, "\0"
73 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
75 * This is the entry of the real U-Boot from a board port
76 * that supports SPL booting on the MPC5200. We only need
77 * to call board_init_f() here. Everything else has already
78 * been done in the SPL u-boot version.
80 GET_GOT /* initialize GOT access */
81 bl board_init_f /* run 1st part of board init code (in Flash)*/
82 /* NOTREACHED - board_init_f() does not return */
84 mfmsr r5 /* save msr contents */
86 /* Move CSBoot and adjust instruction pointer */
87 /*--------------------------------------------------------------*/
89 #if defined(CONFIG_SYS_LOWBOOT)
90 # if defined(CONFIG_SYS_RAMBOOT)
91 # error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
92 # endif /* CONFIG_SYS_RAMBOOT */
93 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
94 lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
95 ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
96 stw r3, 0x4(r4) /* CS0 start */
97 lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
98 ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
99 stw r3, 0x8(r4) /* CS0 stop */
101 ori r3, r3, 0x02010000@l
102 stw r3, 0x54(r4) /* CS0 and Boot enable */
104 lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */
105 ori r3, r3, lowboot_reentry@l /* to the address space the linker used */
110 lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
111 ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
112 stw r3, 0x4c(r4) /* Boot start */
113 lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
114 ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
115 stw r3, 0x50(r4) /* Boot stop */
117 ori r3, r3, 0x02000001@l
118 stw r3, 0x54(r4) /* Boot enable, CS0 disable */
119 #endif /* CONFIG_SYS_LOWBOOT */
121 #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
122 lis r3, CONFIG_SYS_MBAR@h
123 ori r3, r3, CONFIG_SYS_MBAR@l
124 /* MBAR is mirrored into the MBAR SPR */
126 rlwinm r3, r3, 16, 16, 31
127 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
129 #endif /* CONFIG_SYS_DEFAULT_MBAR */
131 /* Initialise the MPC5xxx processor core */
132 /*--------------------------------------------------------------*/
136 /* initialize some things that are hard to access from C */
137 /*--------------------------------------------------------------*/
139 /* set up stack in on-chip SRAM */
140 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
141 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
142 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
143 li r0, 0 /* Make room for stack frame header and */
144 stwu r0, -4(r1) /* clear final stack frame so that */
145 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
147 /* let the C-code set up the rest */
149 /* Be careful to keep code relocatable ! */
150 /*--------------------------------------------------------------*/
152 #ifndef CONFIG_SPL_BUILD
153 GET_GOT /* initialize GOT access */
157 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
159 bl board_init_f /* run 1st part of board init code (in Flash)*/
161 /* NOTREACHED - board_init_f() does not return */
164 #ifndef CONFIG_SPL_BUILD
169 .globl _start_of_vectors
173 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
175 /* Data Storage exception. */
176 STD_EXCEPTION(0x300, DataStorage, UnknownException)
178 /* Instruction Storage exception. */
179 STD_EXCEPTION(0x400, InstStorage, UnknownException)
181 /* External Interrupt exception. */
182 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
184 /* Alignment exception. */
187 EXCEPTION_PROLOG(SRR0, SRR1)
192 addi r3,r1,STACK_FRAME_OVERHEAD
193 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
195 /* Program check exception */
198 EXCEPTION_PROLOG(SRR0, SRR1)
199 addi r3,r1,STACK_FRAME_OVERHEAD
200 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
203 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
205 /* I guess we could implement decrementer, and may have
206 * to someday for timekeeping.
208 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
210 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
211 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
212 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
213 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
215 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
216 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
218 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
219 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
220 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
224 * This exception occurs when the program counter matches the
225 * Instruction Address Breakpoint Register (IABR).
227 * I want the cpu to halt if this occurs so I can hunt around
228 * with the debugger and look at things.
230 * When DEBUG is defined, both machine check enable (in the MSR)
231 * and checkstop reset enable (in the reset mode register) are
232 * turned off and so a checkstop condition will result in the cpu
235 * I force the cpu into a checkstop condition by putting an illegal
236 * instruction here (at least this is the theory).
238 * well - that didnt work, so just do an infinite loop!
242 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
244 STD_EXCEPTION(0x1400, SMI, UnknownException)
246 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
247 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
248 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
249 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
250 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
251 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
252 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
253 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
254 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
255 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
256 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
257 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
258 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
259 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
260 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
261 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
262 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
263 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
264 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
265 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
266 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
267 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
268 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
269 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
270 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
271 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
272 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
275 .globl _end_of_vectors
281 * This code finishes saving the registers to the exception frame
282 * and jumps to the appropriate handler for the exception.
283 * Register r21 is pointer into trap frame, r1 has new stack pointer.
285 .globl transfer_to_handler
296 andi. r24,r23,0x3f00 /* get vector offset */
300 lwz r24,0(r23) /* virtual address of handler */
301 lwz r23,4(r23) /* where to go when done */
306 rfi /* jump to handler, enable MMU */
309 mfmsr r28 /* Disable interrupts */
313 SYNC /* Some chip revs need this... */
328 lwz r2,_NIP(r1) /* Restore environment */
337 #endif /* CONFIG_SPL_BUILD */
340 * This code initialises the MPC5xxx processor core
341 * (conforms to PowerPC 603e spec)
342 * Note: expects original MSR contents to be in r5.
348 /* Initialize machine status; enable machine check interrupt */
349 /*--------------------------------------------------------------*/
351 li r3, MSR_KERNEL /* Set ME and RI flags */
352 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
354 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
356 SYNC /* Some chip revs need this... */
359 mtspr SRR1, r3 /* Make SRR1 match MSR */
361 /* Initialize the Hardware Implementation-dependent Registers */
362 /* HID0 also contains cache control */
363 /*--------------------------------------------------------------*/
365 lis r3, CONFIG_SYS_HID0_INIT@h
366 ori r3, r3, CONFIG_SYS_HID0_INIT@l
370 lis r3, CONFIG_SYS_HID0_FINAL@h
371 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
375 /* clear all BAT's */
376 /*--------------------------------------------------------------*/
413 /* invalidate all tlb's */
415 /* From the 603e User Manual: "The 603e provides the ability to */
416 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
417 /* instruction invalidates the TLB entry indexed by the EA, and */
418 /* operates on both the instruction and data TLBs simultaneously*/
419 /* invalidating four TLB entries (both sets in each TLB). The */
420 /* index corresponds to bits 15-19 of the EA. To invalidate all */
421 /* entries within both TLBs, 32 tlbie instructions should be */
422 /* issued, incrementing this field by one each time." */
424 /* "Note that the tlbia instruction is not implemented on the */
427 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
428 /* incrementing by 0x1000 each time. The code below is sort of */
429 /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
431 /*--------------------------------------------------------------*/
442 /*--------------------------------------------------------------*/
448 * Note: requires that all cache bits in
449 * HID0 are in the low half word.
456 ori r4, r4, HID0_ILOCK
458 ori r4, r3, HID0_ICFI
460 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
462 mtspr HID0, r3 /* clears invalidate */
465 .globl icache_disable
469 ori r4, r4, HID0_ICE|HID0_ILOCK
471 ori r4, r3, HID0_ICFI
473 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
475 mtspr HID0, r3 /* clears invalidate */
481 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
489 ori r4, r4, HID0_DLOCK
493 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
495 mtspr HID0, r3 /* clears invalidate */
498 .globl dcache_disable
502 ori r4, r4, HID0_DCE|HID0_DLOCK
506 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
508 mtspr HID0, r3 /* clears invalidate */
514 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
527 #ifndef CONFIG_SPL_BUILD
528 /*------------------------------------------------------------------------------*/
531 * void relocate_code (addr_sp, gd, addr_moni)
533 * This "function" does not return, instead it continues in RAM
534 * after relocating the monitor code.
538 * r5 = length in bytes
543 mr r1, r3 /* Set new stack pointer */
544 mr r9, r4 /* Save copy of Global Data pointer */
545 mr r10, r5 /* Save copy of Destination Address */
548 mr r3, r5 /* Destination Address */
549 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
550 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
551 lwz r5, GOT(__init_end)
553 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
558 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
564 /* First our own GOT */
566 /* then the one used by the C code */
576 beq cr1,4f /* In place copy is not necessary */
577 beq 7f /* Protect against 0 count */
596 * Now flush the cache: note that we must start from a cache aligned
597 * address. Otherwise we might miss one cache line.
601 beq 7f /* Always flush prefetch queue in any case */
604 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
605 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
613 sync /* Wait for all dcbst to complete on bus */
614 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
615 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
623 7: sync /* Wait for all icbi to complete on bus */
627 * We are done. Do not return, instead branch to second part of board
628 * initialization, now running from RAM.
631 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
638 * Relocation Function, r12 point to got2+0x8000
640 * Adjust got2 pointers, no need to check for 0, this code
641 * already puts a few entries in the table.
643 li r0,__got2_entries@sectoff@l
644 la r3,GOT(_GOT2_TABLE_)
645 lwz r11,GOT(_GOT2_TABLE_)
657 * Now adjust the fixups and the pointers to the fixups
658 * in case we need to move ourselves again.
660 li r0,__fixup_entries@sectoff@l
661 lwz r3,GOT(_FIXUP_TABLE_)
677 * Now clear BSS segment
679 lwz r3,GOT(__bss_start)
680 lwz r4,GOT(__bss_end)
693 mr r3, r9 /* Global Data pointer */
694 mr r4, r10 /* Destination Address */
698 * Copy exception vector code to low memory
701 * r7: source address, r8: end address, r9: target address
705 mflr r4 /* save link register */
708 lwz r8, GOT(_end_of_vectors)
710 li r9, 0x100 /* reset vector always at 0x100 */
713 bgelr /* return if r7>=r8 - just in case */
723 * relocate `hdlr' and `int_return' entries
725 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
726 li r8, Alignment - _start + EXC_OFF_SYS_RESET
729 addi r7, r7, 0x100 /* next exception vector */
733 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
736 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
739 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
740 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
743 addi r7, r7, 0x100 /* next exception vector */
747 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
748 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
751 addi r7, r7, 0x100 /* next exception vector */
755 mfmsr r3 /* now that the vectors have */
756 lis r7, MSR_IP@h /* relocated into low memory */
757 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
758 andc r3, r3, r7 /* (if it was on) */
759 SYNC /* Some chip revs need this... */
763 mtlr r4 /* restore link register */
766 #endif /* CONFIG_SPL_BUILD */