2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/cpm_8260.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
16 extern unsigned long board_get_cpu_clk_f (void);
19 static void config_8260_ioports (volatile immap_t * immr)
23 for (portnum = 0; portnum < 4; portnum++) {
30 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
31 iop_conf_t *eiopc = iopc + 32;
36 * index 0 refers to pin 31,
37 * index 31 refers to pin 0
39 while (iopc < eiopc) {
59 volatile ioport_t *iop = ioport_addr (immr, portnum);
63 * the (somewhat confused) paragraph at the
64 * bottom of page 35-5 warns that there might
65 * be "unknown behaviour" when programming
66 * PSORx and PDIRx, if PPARx = 1, so I
67 * decided this meant I had to disable the
68 * dedicated function first, and enable it
72 iop->psor = (iop->psor & tpmsk) | psor;
73 iop->podr = (iop->podr & tpmsk) | podr;
74 iop->pdat = (iop->pdat & tpmsk) | pdat;
75 iop->pdir = (iop->pdir & tpmsk) | pdir;
81 #define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
83 * Breath some life into the CPU...
85 * Set up the memory map,
86 * initialize a bunch of registers,
87 * initialize the UPM's
89 void cpu_init_f (volatile immap_t * immr)
91 #if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
94 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
95 unsigned long cpu_clk;
97 volatile memctl8260_t *memctl = &immr->im_memctl;
98 extern void m8260_cpm_reset (void);
100 /* Pointer is writable since we allocated a register for it */
101 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
103 /* Clear initial global data */
104 memset ((void *) gd, 0, sizeof (gd_t));
106 /* RSR - Reset Status Register - clear all status (5-4) */
107 gd->arch.reset_status = immr->im_clkrst.car_rsr;
108 immr->im_clkrst.car_rsr = RSR_ALLBITS;
110 /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
111 immr->im_clkrst.car_rmr = CONFIG_SYS_RMR;
113 /* BCR - Bus Configuration Register (4-25) */
114 #if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE)
115 if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
116 immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010);
118 immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010);
121 immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR;
124 /* SIUMCR - contains debug pin configuration (4-31) */
125 #if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH)
126 cpu_clk = board_get_cpu_clk_f ();
127 if (cpu_clk >= 100000000) {
128 immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000);
130 immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000);
133 immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
136 config_8260_ioports (immr);
138 /* initialize time counter status and control register (4-40) */
139 immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC;
141 /* initialize the PIT (4-42) */
142 immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
144 #if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
145 /* System clock control register (9-8) */
146 sccr = immr->im_clkrst.car_sccr &
147 (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
148 immr->im_clkrst.car_sccr = sccr |
149 (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
150 #endif /* !CONFIG_COGENT */
156 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
157 * addresses - these have to be modified later when FLASH size
158 * has been determined
161 #if defined(CONFIG_SYS_OR0_REMAP)
162 memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
164 #if defined(CONFIG_SYS_OR1_REMAP)
165 memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
168 /* now restrict to preliminary range */
169 /* the PS came from the HRCW, don't change it */
170 memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK);
171 memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
173 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
174 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
175 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
178 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
179 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
180 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
183 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
184 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
185 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
188 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
189 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
190 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
193 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
194 memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
195 memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
198 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
199 memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
200 memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
203 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
204 memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
205 memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
208 #if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM)
209 memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM;
210 memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM;
213 #if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM)
214 memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM;
215 memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM;
218 #if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM)
219 memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM;
220 memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM;
223 #if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM)
224 memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM;
225 memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM;
232 * initialize higher level parts of CPU like time base and timers
234 int cpu_init_r (void)
236 volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;
238 immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
244 * print out the reason for the reset
246 int prt_8260_rsr (void)
254 RSR_CSRS, "Check Stop"}, {
255 RSR_SWRS, "Software Watchdog"}, {
256 RSR_BMRS, "Bus Monitor"}, {
257 RSR_ESRS, "External Soft"}, {
258 RSR_EHRS, "External Hard"}
260 static int n = sizeof bits / sizeof bits[0];
261 ulong rsr = gd->arch.reset_status;
265 puts (CPU_ID_STR " Reset Status:");
268 for (i = 0; i < n; i++)
269 if (rsr & bits[i].mask) {
270 printf ("%s%s", sep, bits[i].desc);