2 * MPC8260 FCC Fast Ethernet
4 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MPC8260 FCC Fast Ethernet
30 * Basic ET HW initialization and packet RX/TX routines
32 * This code will not perform the IO port configuration. This should be
33 * done in the iop_conf_t structure specific for the board.
36 * add a PHY driver to do the negotiation
37 * reflect negotiation results in FPSMR
38 * look for ways to configure the board specific stuff elsewhere, eg.
39 * config_xxx.h or the board directory
44 #include <asm/cpm_8260.h>
50 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
54 DECLARE_GLOBAL_DATA_PTR;
56 #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
58 static struct ether_fcc_info_s
62 ulong cpm_cr_enet_sblock;
63 ulong cpm_cr_enet_page;
69 #ifdef CONFIG_ETHER_ON_FCC1
75 CONFIG_SYS_CMXFCR_MASK1,
76 CONFIG_SYS_CMXFCR_VALUE1
80 #ifdef CONFIG_ETHER_ON_FCC2
86 CONFIG_SYS_CMXFCR_MASK2,
87 CONFIG_SYS_CMXFCR_VALUE2
91 #ifdef CONFIG_ETHER_ON_FCC3
97 CONFIG_SYS_CMXFCR_MASK3,
98 CONFIG_SYS_CMXFCR_VALUE3
103 /*---------------------------------------------------------------------*/
105 /* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
106 #define PKT_MAXDMA_SIZE 1520
108 /* The FCC stores dest/src/type, data, and checksum for receive packets. */
109 #define PKT_MAXBUF_SIZE 1518
110 #define PKT_MINBUF_SIZE 64
112 /* Maximum input buffer size. Must be a multiple of 32. */
113 #define PKT_MAXBLR_SIZE 1536
115 #define TOUT_LOOP 1000000
119 static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8)));
121 #error "txbuf must be 64-bit aligned"
124 static uint rxIdx; /* index of the current RX buffer */
125 static uint txIdx; /* index of the current TX buffer */
128 * FCC Ethernet Tx and Rx buffer descriptors.
129 * Provide for Double Buffering
130 * Note: PKTBUFSRX is defined in net.h
133 typedef volatile struct rtxbd {
134 cbd_t rxbd[PKTBUFSRX];
135 cbd_t txbd[TX_BUF_CNT];
138 /* Good news: the FCC supports external BDs! */
140 static RTXBD rtx __attribute__ ((aligned(8)));
142 #error "rtx must be 64-bit aligned"
145 static int fec_send(struct eth_device *dev, void *packet, int length)
151 printf("fec: bad packet size: %d\n", length);
155 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
156 if (i >= TOUT_LOOP) {
157 puts ("fec: tx buffer not ready\n");
162 rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
163 rtx.txbd[txIdx].cbd_datlen = length;
164 rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
167 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
168 if (i >= TOUT_LOOP) {
169 puts ("fec: tx error\n");
175 printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc);
178 /* return only status bits */
179 result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
185 static int fec_recv(struct eth_device* dev)
191 if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
193 break; /* nothing received - leave for() loop */
195 length = rtx.rxbd[rxIdx].cbd_datlen;
197 if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
198 printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
201 /* Pass the packet up to the protocol layers. */
202 NetReceive(NetRxPackets[rxIdx], length - 4);
206 /* Give the buffer back to the FCC. */
207 rtx.rxbd[rxIdx].cbd_datlen = 0;
209 /* wrap around buffer index when necessary */
210 if ((rxIdx + 1) >= PKTBUFSRX) {
211 rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
215 rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
223 static int fec_init(struct eth_device* dev, bd_t *bis)
225 struct ether_fcc_info_s * info = dev->priv;
227 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
228 volatile cpm8260_t *cp = &(immr->im_cpm);
229 fcc_enet_t *pram_ptr;
230 unsigned long mem_addr;
236 /* 28.9 - (1-2): ioports have been set up already */
238 /* 28.9 - (3): connect FCC's tx and rx clocks */
239 immr->im_cpmux.cmx_uar = 0;
240 immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
243 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
244 immr->im_fcc[info->ether_index].fcc_gfmr =
245 FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
247 /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
248 immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
250 /* 28.9 - (6): FDSR: Ethernet Syn */
251 immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
253 /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
257 /* Setup Receiver Buffer Descriptors */
258 for (i = 0; i < PKTBUFSRX; i++)
260 rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
261 rtx.rxbd[i].cbd_datlen = 0;
262 rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
264 rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
266 /* Setup Ethernet Transmitter Buffer Descriptors */
267 for (i = 0; i < TX_BUF_CNT; i++)
269 rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
270 rtx.txbd[i].cbd_datlen = 0;
271 rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
273 rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
275 /* 28.9 - (7): initialise parameter ram */
276 pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
278 /* clear whole structure to make sure all reserved fields are zero */
279 memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
282 * common Parameter RAM area
284 * Allocate space in the reserved FCC area of DPRAM for the
285 * internal buffers. No one uses this space (yet), so we
286 * can do this. Later, we will add resource management for
289 mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
290 pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
291 pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
293 * Set maximum bytes per receive buffer.
294 * It must be a multiple of 32.
296 pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
297 pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
298 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
299 pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
300 pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
301 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
302 pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
304 /* protocol-specific area */
305 pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
306 pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
307 pram_ptr->fen_retlim = 15; /* Retry limit threshold */
308 pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
310 * Set Ethernet station address.
312 * This is supplied in the board information structure, so we
313 * copy that into the controller.
314 * So, far we have only been given one Ethernet address. We make
315 * it unique by setting a few bits in the upper byte of the
316 * non-static part of the address.
318 #define ea eth_get_dev()->enetaddr
319 pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
320 pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
321 pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
323 pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
324 /* pad pointer. use tiptr since we don't need a specific padding char */
325 pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
326 pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
327 pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
328 pram_ptr->fen_rfthr = 1;
329 pram_ptr->fen_rfcnt = 1;
331 printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n",
332 pram_ptr->fen_genfcc.fcc_rbase);
333 printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n",
334 pram_ptr->fen_genfcc.fcc_tbase);
337 /* 28.9 - (8): clear out events in FCCE */
338 immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
340 /* 28.9 - (9): FCCM: mask all events */
341 immr->im_fcc[info->ether_index].fcc_fccm = 0;
343 /* 28.9 - (10-12): we don't use ethernet interrupts */
347 * Let's re-initialize the channel now. We have to do it later
348 * than the manual describes because we have just now finished
349 * the BD initialization.
351 cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
352 info->cpm_cr_enet_sblock,
354 CPM_CR_INIT_TRX) | CPM_CR_FLG;
356 __asm__ __volatile__ ("eieio");
357 } while (cp->cp_cpcr & CPM_CR_FLG);
359 /* 28.9 - (14): enable tx/rx in gfmr */
360 immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
365 static void fec_halt(struct eth_device* dev)
367 struct ether_fcc_info_s * info = dev->priv;
368 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
370 /* write GFMR: disable tx/rx */
371 immr->im_fcc[info->ether_index].fcc_gfmr &=
372 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
375 int fec_initialize(bd_t *bis)
377 struct eth_device* dev;
380 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
382 dev = (struct eth_device*) malloc(sizeof *dev);
383 memset(dev, 0, sizeof *dev);
385 sprintf(dev->name, "FCC%d",
386 ether_fcc_info[i].ether_index + 1);
387 dev->priv = ðer_fcc_info[i];
388 dev->init = fec_init;
389 dev->halt = fec_halt;
390 dev->send = fec_send;
391 dev->recv = fec_recv;
395 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
396 && defined(CONFIG_BITBANGMII)
397 miiphy_register(dev->name,
398 bb_miiphy_read, bb_miiphy_write);
405 #ifdef CONFIG_ETHER_LOOPBACK_TEST
407 #define ELBT_BUFSZ 1024 /* must be multiple of 32 */
411 #define ELBT_NRXBD 4 /* must be at least 2 */
414 #define ELBT_MAXRXERR 32
415 #define ELBT_MAXTXERR 32
417 #define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */
428 uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl;
429 uint badsrc, badtyp, badlen, badbit;
433 static elbt_prdesc rxeacc_descs[] = {
434 { offsetof(elbt_rxeacc, _l), "Not Last in Frame" },
435 { offsetof(elbt_rxeacc, _f), "Not First in Frame" },
436 { offsetof(elbt_rxeacc, m), "Address Miss" },
437 { offsetof(elbt_rxeacc, bc), "Broadcast Address" },
438 { offsetof(elbt_rxeacc, mc), "Multicast Address" },
439 { offsetof(elbt_rxeacc, lg), "Frame Length Violation"},
440 { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" },
441 { offsetof(elbt_rxeacc, sh), "Short Frame" },
442 { offsetof(elbt_rxeacc, cr), "CRC Error" },
443 { offsetof(elbt_rxeacc, ov), "Overrun" },
444 { offsetof(elbt_rxeacc, cl), "Collision" },
445 { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" },
446 { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" },
447 { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" },
448 { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" },
450 static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
454 uint def, hb, lc, rl, rc, un, csl;
458 static elbt_prdesc txeacc_descs[] = {
459 { offsetof(elbt_txeacc, def), "Defer Indication" },
460 { offsetof(elbt_txeacc, hb), "Heartbeat" },
461 { offsetof(elbt_txeacc, lc), "Late Collision" },
462 { offsetof(elbt_txeacc, rl), "Retransmission Limit" },
463 { offsetof(elbt_txeacc, rc), "Retry Count" },
464 { offsetof(elbt_txeacc, un), "Underrun" },
465 { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" },
467 static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
471 uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ];
472 uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ];
473 cbd_t rxbd[ELBT_NRXBD];
474 cbd_t txbd[ELBT_NTXBD];
475 enum { Idle, Running, Closing, Closed } state;
476 int proff, page, sblock;
477 uint clstime, nsent, ntxerr, nrcvd, nrxerr;
478 ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR];
481 } __attribute__ ((aligned(8)))
484 static uchar patbytes[ELBT_NTXBD] = {
485 0xff, 0xaa, 0x55, 0x00
487 static uint patwords[ELBT_NTXBD] = {
488 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000
492 static elbt_chan elbt_chans[3] __attribute__ ((aligned(8)));
494 #error "elbt_chans must be 64-bit aligned"
497 #define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005)
499 static elbt_prdesc epram_descs[] = {
500 { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" },
501 { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" },
502 { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" },
503 { offsetof(fcc_enet_t, fen_octc), "Octets" },
504 { offsetof(fcc_enet_t, fen_colc), "Collisions" },
505 { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" },
506 { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" },
507 { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" },
508 { offsetof(fcc_enet_t, fen_frgc), "Fragments" },
509 { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" },
510 { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" },
511 { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" },
512 { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" },
513 { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" },
514 { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" },
515 { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" },
516 { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"},
518 static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
521 * given an elbt_prdesc array and an array of base addresses, print
522 * each prdesc down the screen with the values fetched from each
523 * base address across the screen
526 print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase)
528 elbt_prdesc *dp = descs, *edp = dp + ndesc;
533 for (i = 0; i < nbase; i++)
534 printf (" Channel %d", i);
540 printf ("%-32s", dp->lab);
542 for (i = 0; i < nbase; i++) {
543 uint val = *(uint *)(bases[i] + dp->off);
545 printf (" %10u", val);
555 * return number of bits that are set in a value; value contains
556 * nbits (right-justified) bits.
558 static uint __inline__
559 nbs (uint value, uint nbits)
563 uint pos = sizeof (uint) * 8;
565 __asm__ __volatile__ ("\
567 1: rlwnm. %2,%1,%4,31,31\n\
573 : "r"(value), "r"(nbits), "r"(cnt), "r"(pos)
589 badbits (uchar *bp, int n, ulong pat)
594 while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) {
597 diff = *bp++ ^ (uchar)pat;
600 cnt += nbs ((ulong)diff, 8);
606 nl = n / sizeof (ulong);
607 n -= nl * sizeof (ulong);
615 cnt += nbs (diff, 32);
625 diff = *bp++ ^ (uchar)pat;
628 cnt += nbs ((ulong)diff, 8);
636 static inline unsigned short
637 swap16 (unsigned short x)
639 return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
642 /* broadcast is not an error - we send them like that */
643 #define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC)
646 eth_loopback_test (void)
648 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
649 volatile cpm8260_t *cp = &(immr->im_cpm);
651 ulong runtime, nmsec;
654 puts ("FCC Ethernet External loopback test\n");
656 eth_getenv_enetaddr("ethaddr", NetOurEther);
659 * global initialisations for all FCC channels
662 /* 28.9 - (1-2): ioports have been set up already */
664 #if defined(CONFIG_HYMOD)
666 * Attention: this is board-specific
671 # define FCC_START_LOOP 0
672 # define FCC_END_LOOP 2
675 * Attention: this is board-specific
676 * - FCC1 Rx-CLK is CLK10
677 * - FCC1 Tx-CLK is CLK11
678 * - FCC2 Rx-CLK is CLK13
679 * - FCC2 Tx-CLK is CLK14
680 * - FCC3 Rx-CLK is CLK15
681 * - FCC3 Tx-CLK is CLK16
684 /* 28.9 - (3): connect FCC's tx and rx clocks */
685 immr->im_cpmux.cmx_uar = 0;
686 immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
687 CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
688 CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
689 #elif defined(CONFIG_SACSng)
691 * Attention: this is board-specific
694 # define FCC_START_LOOP 1
695 # define FCC_END_LOOP 1
698 * Attention: this is board-specific
699 * - FCC2 Rx-CLK is CLK13
700 * - FCC2 Tx-CLK is CLK14
703 /* 28.9 - (3): connect FCC's tx and rx clocks */
704 immr->im_cpmux.cmx_uar = 0;
705 immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
707 #error "eth_loopback_test not supported on your board"
710 puts ("Initialise FCC channels:");
712 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
713 elbt_chan *ecp = &elbt_chans[c];
714 volatile fcc_t *fcp = &immr->im_fcc[c];
715 volatile fcc_enet_t *fpp;
720 * initialise channel data
725 memset ((void *)ecp, 0, sizeof (*ecp));
732 ecp->proff = PROFF_FCC1;
733 ecp->page = CPM_CR_FCC1_PAGE;
734 ecp->sblock = CPM_CR_FCC1_SBLOCK;
738 ecp->proff = PROFF_FCC2;
739 ecp->page = CPM_CR_FCC2_PAGE;
740 ecp->sblock = CPM_CR_FCC2_SBLOCK;
744 ecp->proff = PROFF_FCC3;
745 ecp->page = CPM_CR_FCC3_PAGE;
746 ecp->sblock = CPM_CR_FCC3_SBLOCK;
751 * set up tx buffers and bds
754 for (i = 0; i < ELBT_NTXBD; i++) {
755 cbd_t *bdp = &ecp->txbd[i];
756 uchar *bp = &ecp->txbufs[i][0];
758 bdp->cbd_bufaddr = (uint)bp;
760 bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ;
761 bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \
762 BD_ENET_TX_LAST | BD_ENET_TX_TC;
764 memset ((void *)bp, patbytes[i], ELBT_BUFSZ);
765 NetSetEther (bp, NetBcastAddr, 0x8000);
767 ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP;
770 * set up rx buffers and bds
773 for (i = 0; i < ELBT_NRXBD; i++) {
774 cbd_t *bdp = &ecp->rxbd[i];
775 uchar *bp = &ecp->rxbufs[i][0];
777 bdp->cbd_bufaddr = (uint)bp;
779 bdp->cbd_sc = BD_ENET_RX_EMPTY;
781 memset ((void *)bp, 0, ELBT_BUFSZ);
783 ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP;
786 * set up the FCC channel hardware
789 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
790 fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
792 /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */
793 fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \
794 FCC_PSMR_ENCRC | FCC_PSMR_PRO | \
795 FCC_PSMR_MON | FCC_PSMR_RSH;
797 /* 28.9 - (6): FDSR: Ethernet Syn */
798 fcp->fcc_fdsr = 0xD555;
800 /* 29.9 - (7): initialise parameter ram */
801 fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]);
803 /* clear whole struct to make sure all resv fields are zero */
804 memset ((void *)fpp, 0, sizeof (fcc_enet_t));
807 * common Parameter RAM area
809 * Allocate space in the reserved FCC area of DPRAM for the
810 * internal buffers. No one uses this space (yet), so we
811 * can do this. Later, we will add resource management for
814 addr = CPM_FCC_SPECIAL_BASE + (c * 64);
815 fpp->fen_genfcc.fcc_riptr = addr;
816 fpp->fen_genfcc.fcc_tiptr = addr + 32;
819 * Set maximum bytes per receive buffer.
820 * It must be a multiple of 32.
821 * buffers are in 60x bus memory.
823 fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
824 fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
825 fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]);
826 fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
827 fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]);
829 /* protocol-specific area */
830 fpp->fen_cmask = 0xdebb20e3; /* CRC mask */
831 fpp->fen_cpres = 0xffffffff; /* CRC preset */
832 fpp->fen_retlim = 15; /* Retry limit threshold */
833 fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */
836 * Set Ethernet station address.
838 * This is supplied in the board information structure, so we
839 * copy that into the controller.
840 * So, far we have only been given one Ethernet address. We use
841 * the same address for all channels
843 #define ea NetOurEther
844 fpp->fen_paddrh = (ea[5] << 8) + ea[4];
845 fpp->fen_paddrm = (ea[3] << 8) + ea[2];
846 fpp->fen_paddrl = (ea[1] << 8) + ea[0];
849 fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */
851 * pad pointer. use tiptr since we don't need
852 * a specific padding char
854 fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr;
855 fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */
856 fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */
860 /* 28.9 - (8): clear out events in FCCE */
861 fcp->fcc_fcce = ~0x0;
863 /* 28.9 - (9): FCCM: mask all events */
866 /* 28.9 - (10-12): we don't use ethernet interrupts */
870 * Let's re-initialize the channel now. We have to do it later
871 * than the manual describes because we have just now finished
872 * the BD initialization.
874 cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \
875 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG;
877 __asm__ __volatile__ ("eieio");
878 } while (cp->cp_cpcr & CPM_CR_FLG);
881 puts (" done\nStarting test... (Ctrl-C to Finish)\n");
884 * Note: don't want serial output from here until the end of the
885 * test - the delays would probably stuff things up.
889 runtime = get_timer (0);
894 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
895 volatile fcc_t *fcp = &immr->im_fcc[c];
896 elbt_chan *ecp = &elbt_chans[c];
899 switch (ecp->state) {
903 * set the channel Running ...
906 /* 28.9 - (14): enable tx/rx in gfmr */
907 fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
909 ecp->state = Running;
914 * (while Running only) check for
915 * termination of the test
922 * initiate a "graceful stop transmit"
925 cp->cp_cpcr = mk_cr_cmd (ecp->page, \
927 CPM_CR_GRACEFUL_STOP_TX) | \
930 __asm__ __volatile__ ("eieio");
931 } while (cp->cp_cpcr & CPM_CR_FLG);
933 ecp->clstime = get_timer (0);
934 ecp->state = Closing;
936 /* fall through ... */
940 * (while Running or Closing) poll the channel:
941 * - check for any non-READY tx buffers and
943 * - check for any non-EMPTY rx buffers and
944 * check that they were received correctly,
945 * adjust counters etc, then make empty
948 for (i = 0; i < ELBT_NTXBD; i++) {
949 cbd_t *bdp = &ecp->txbd[i];
950 ushort sc = bdp->cbd_sc;
952 if ((sc & BD_ENET_TX_READY) != 0)
956 * this frame has finished
961 if (sc & BD_ENET_TX_STATS) {
969 if (n < ELBT_MAXTXERR)
972 if (sc & BD_ENET_TX_DEF)
974 if (sc & BD_ENET_TX_HB)
976 if (sc & BD_ENET_TX_LC)
978 if (sc & BD_ENET_TX_RL)
980 if (sc & BD_ENET_TX_RCMASK)
982 if (sc & BD_ENET_TX_UN)
984 if (sc & BD_ENET_TX_CSL)
991 if (ecp->state == Closing)
992 ecp->clstime = get_timer (0);
994 /* make it ready again */
995 bdp->cbd_sc |= BD_ENET_TX_READY;
998 for (i = 0; i < ELBT_NRXBD; i++) {
999 cbd_t *bdp = &ecp->rxbd[i];
1000 ushort sc = bdp->cbd_sc, mask;
1002 if ((sc & BD_ENET_RX_EMPTY) != 0)
1005 /* we have a new frame in this buffer */
1008 mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST;
1009 if ((sc & mask) != mask) {
1010 /* somethings wrong here ... */
1011 if (!(sc & BD_ENET_RX_LAST))
1013 if (!(sc & BD_ENET_RX_FIRST))
1017 if (sc & BD_ENET_RX_ERRS) {
1021 * we had some sort of error
1025 if (n < ELBT_MAXRXERR)
1026 ecp->rxerrs[n] = sc;
1028 if (sc & BD_ENET_RX_MISS)
1030 if (sc & BD_ENET_RX_BC)
1032 if (sc & BD_ENET_RX_MC)
1034 if (sc & BD_ENET_RX_LG)
1036 if (sc & BD_ENET_RX_NO)
1038 if (sc & BD_ENET_RX_SH)
1040 if (sc & BD_ENET_RX_CR)
1042 if (sc & BD_ENET_RX_OV)
1044 if (sc & BD_ENET_RX_CL)
1051 ushort datlen = bdp->cbd_datlen;
1054 int ours, tb, n, nbytes;
1056 ehp = (Ethernet_t *) \
1059 ours = memcmp (ehp->et_src, \
1062 prot = swap16 (ehp->et_protlen);
1066 nbytes = ELBT_BUFSZ - \
1067 offsetof (Ethernet_t, \
1071 /* check the frame is correct */
1072 if (datlen != ELBT_BUFSZ)
1073 ecp->rxeacc.badlen++;
1075 ecp->rxeacc.badsrc++;
1076 else if (!tb || n >= ELBT_NTXBD)
1077 ecp->rxeacc.badtyp++;
1088 ecp->rxeacc.badbit += \
1093 if (ecp->state == Closing)
1094 ecp->clstime = get_timer (0);
1096 /* make it empty again */
1097 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
1100 if (ecp->state != Closing)
1104 * (while Closing) check to see if
1105 * waited long enough
1108 if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) {
1109 /* write GFMR: disable tx/rx */
1111 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
1112 ecp->state = Closed;
1123 } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1));
1125 runtime = get_timer (runtime);
1126 if (runtime <= ELBT_CLSWAIT) {
1127 printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n",
1128 runtime, ELBT_CLSWAIT);
1131 nmsec = runtime - ELBT_CLSWAIT;
1133 printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n",
1134 nmsec, ELBT_CLSWAIT);
1140 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
1141 elbt_chan *ecp = &elbt_chans[c];
1142 uint rxpps, txpps, nerr;
1144 rxpps = (ecp->nrcvd * 1000) / nmsec;
1145 txpps = (ecp->nsent * 1000) / nmsec;
1147 printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), "
1148 "%d sent (%d pps, %d txerrs)\n\n", c,
1149 ecp->nrcvd, rxpps, ecp->nrxerr,
1150 ecp->nsent, txpps, ecp->ntxerr);
1152 if ((nerr = ecp->nrxerr) > 0) {
1155 printf ("\tFirst %d rx errs:", nerr);
1156 for (i = 0; i < nerr; i++)
1157 printf (" %04x", ecp->rxerrs[i]);
1161 if ((nerr = ecp->ntxerr) > 0) {
1164 printf ("\tFirst %d tx errs:", nerr);
1165 for (i = 0; i < nerr; i++)
1166 printf (" %04x", ecp->txerrs[i]);
1171 puts ("Receive Error Counts:\n");
1172 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1173 bases[c] = (uchar *)&elbt_chans[c].rxeacc;
1174 print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
1176 puts ("\nTransmit Error Counts:\n");
1177 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1178 bases[c] = (uchar *)&elbt_chans[c].txeacc;
1179 print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
1181 puts ("\nRMON(-like) Counters:\n");
1182 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1183 bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
1184 print_desc (epram_descs, epram_ndesc, bases, 3);
1187 #endif /* CONFIG_ETHER_LOOPBACK_TEST */