4 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * (C) Copyright (c) 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
13 * Modified so that it plays nicely when more than one ETHERNET interface
14 * is in use a la ether_fcc.c.
16 * DENX Software Engineerin GmbH
17 * Gary Jennejohn <garyj@denx.de>
19 * See file CREDITS for list of people who contributed to this
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/cpm_8260.h>
46 #if (CONFIG_ETHER_INDEX == 1)
47 # define PROFF_ENET PROFF_SCC1
48 # define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE
49 # define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK
50 # define CMXSCR_MASK (CMXSCR_SC1 |\
54 #elif (CONFIG_ETHER_INDEX == 2)
55 # define PROFF_ENET PROFF_SCC2
56 # define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE
57 # define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK
58 # define CMXSCR_MASK (CMXSCR_SC2 |\
62 #elif (CONFIG_ETHER_INDEX == 3)
63 # define PROFF_ENET PROFF_SCC3
64 # define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE
65 # define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK
66 # define CMXSCR_MASK (CMXSCR_SC3 |\
69 #elif (CONFIG_ETHER_INDEX == 4)
70 # define PROFF_ENET PROFF_SCC4
71 # define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE
72 # define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK
73 # define CMXSCR_MASK (CMXSCR_SC4 |\
80 /* Ethernet Transmit and Receive Buffers */
81 #define DBUF_LENGTH 1520
85 #if !defined(CONFIG_SYS_SCC_TOUT_LOOP)
86 #define CONFIG_SYS_SCC_TOUT_LOOP 1000000
89 static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];
91 static uint rxIdx; /* index of the current RX buffer */
92 static uint txIdx; /* index of the current TX buffer */
95 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
96 * immr->udata_bd address on Dual-Port RAM
97 * Provide for Double Buffering
100 typedef volatile struct CommonBufferDescriptor {
101 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
102 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
108 static int sec_send(struct eth_device *dev, void *packet, int length)
114 printf("scc: bad packet size: %d\n", length);
118 for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
119 if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
120 puts ("scc: tx buffer not ready\n");
125 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
126 rtx->txbd[txIdx].cbd_datlen = length;
127 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
130 for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
131 if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
132 puts ("scc: tx error\n");
137 /* return only status bits */
138 result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
145 static int sec_rx(struct eth_device *dev)
151 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
153 break; /* nothing received - leave for() loop */
156 length = rtx->rxbd[rxIdx].cbd_datlen;
158 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
160 printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
164 /* Pass the packet up to the protocol layers. */
165 NetReceive(NetRxPackets[rxIdx], length - 4);
169 /* Give the buffer back to the SCC. */
170 rtx->rxbd[rxIdx].cbd_datlen = 0;
172 /* wrap around buffer index when necessary */
173 if ((rxIdx + 1) >= PKTBUFSRX) {
174 rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
179 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
186 /**************************************************************
188 * SCC Ethernet Initialization Routine
190 *************************************************************/
192 static int sec_init(struct eth_device *dev, bd_t *bis)
195 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
196 scc_enet_t *pram_ptr;
204 * Assign static pointer to BD area.
205 * Avoid exhausting DPRAM, which would cause a panic.
208 dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16);
209 rtx = (RTXBD *)&immr->im_dprambase[dpaddr];
212 /* 24.21 - (1-3): ioports have been set up already */
214 /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
215 immr->im_cpmux.cmx_uar = 0;
216 immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
217 CONFIG_SYS_CMXSCR_VALUE);
220 /* 24.21 (6) write RBASE and TBASE to parameter RAM */
221 pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
222 pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);
223 pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);
225 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */
226 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */
228 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */
230 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
231 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
234 /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
235 while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
236 immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
239 CPM_CR_INIT_TRX) | CPM_CR_FLG;
241 /* 24.21 - (8-18): Set up parameter RAM */
242 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
243 pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */
244 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
246 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
248 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
250 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
251 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
253 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
254 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
256 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
257 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
258 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
259 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
261 eth_getenv_enetaddr("ethaddr", ea);
262 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
263 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
264 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
266 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
268 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
269 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
270 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
271 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
273 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
274 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
275 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
277 /* 24.21 - (19): Initialize RxBD */
278 for (i = 0; i < PKTBUFSRX; i++)
280 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
281 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
282 rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
285 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
287 /* 24.21 - (20): Initialize TxBD */
288 for (i = 0; i < TX_BUF_CNT; i++)
290 rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD |
293 rtx->txbd[i].cbd_datlen = 0; /* Reset */
294 rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
297 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
299 /* 24.21 - (21): Write 0xffff to SCCE */
300 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0);
302 /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
303 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE |
307 /* 24.21 - (23): we don't use ethernet interrupts */
309 /* 24.21 - (24): Clear GSMR_H to enable normal operations */
310 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0;
312 /* 24.21 - (25): Clear GSMR_L to enable normal operations */
313 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI |
316 SCC_GSMRL_MODE_ENET);
318 /* 24.21 - (26): Initialize DSR */
319 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;
321 /* 24.21 - (27): Initialize PSMR2
325 * NIB = Begin searching for SFD 22 bits after RENA
326 * FDE = Full Duplex Enable
327 * BRO = Reject broadcast packets
328 * PROMISCOUS = Catch all packets regardless of dest. MAC adress
330 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC |
332 #if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
335 #if defined(CONFIG_SCC_ENET_NO_BROADCAST)
338 #if defined(CONFIG_SCC_ENET_PROMISCOUS)
343 /* 24.21 - (28): Write to GSMR_L to enable SCC */
344 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
351 static void sec_halt(struct eth_device *dev)
353 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
354 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
359 static void sec_restart(void)
361 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
362 immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
367 int mpc82xx_scc_enet_initialize(bd_t *bis)
369 struct eth_device *dev;
371 dev = (struct eth_device *) malloc(sizeof *dev);
372 memset(dev, 0, sizeof *dev);
374 sprintf(dev->name, "SCC");
375 dev->init = sec_init;
376 dev->halt = sec_halt;
377 dev->send = sec_send;