2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
7 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
13 #include <mpc8260_irq.h>
14 #include <asm/processor.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 /****************************************************************************/
21 interrupt_handler_t *handler;
26 static struct irq_action irq_handlers[NR_IRQS];
28 static ulong ppc_cached_irq_mask[NR_MASK_WORDS];
30 /****************************************************************************/
31 /* this section was ripped out of arch/powerpc/kernel/ppc8260_pic.c in the */
32 /* Linux/PPC 2.4.x source. There was no copyright notice in that file. */
34 /* The 8260 internal interrupt controller. It is usually
35 * the only interrupt controller.
36 * There are two 32-bit registers (high/low) for up to 64
37 * possible interrupts.
39 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
40 * in a simple arithmetic fashion to mask or pending registers.
41 * That is, interrupt 4 does not map to bit position 4.
42 * We create two tables, indexed by vector number, to indicate
43 * which register to use and which bit in the register to use.
45 static u_char irq_to_siureg[] = {
46 1, 1, 1, 1, 1, 1, 1, 1,
47 1, 1, 1, 1, 1, 1, 1, 1,
48 0, 0, 0, 0, 0, 0, 0, 0,
49 0, 0, 0, 0, 0, 0, 0, 0,
50 1, 1, 1, 1, 1, 1, 1, 1,
51 1, 1, 1, 1, 1, 1, 1, 1,
52 0, 0, 0, 0, 0, 0, 0, 0,
53 0, 0, 0, 0, 0, 0, 0, 0
56 static u_char irq_to_siubit[] = {
57 31, 16, 17, 18, 19, 20, 21, 22,
58 23, 24, 25, 26, 27, 28, 29, 30,
59 29, 30, 16, 17, 18, 19, 20, 21,
60 22, 23, 24, 25, 26, 27, 28, 31,
61 0, 1, 2, 3, 4, 5, 6, 7,
62 8, 9, 10, 11, 12, 13, 14, 15,
63 15, 14, 13, 12, 11, 10, 9, 8,
64 7, 6, 5, 4, 3, 2, 1, 0
67 static void m8260_mask_irq (unsigned int irq_nr)
69 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
73 bit = irq_to_siubit[irq_nr];
74 word = irq_to_siureg[irq_nr];
76 simr = &(immr->im_intctl.ic_simrh);
77 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
78 simr[word] = ppc_cached_irq_mask[word];
81 static void m8260_unmask_irq (unsigned int irq_nr)
83 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
87 bit = irq_to_siubit[irq_nr];
88 word = irq_to_siureg[irq_nr];
90 simr = &(immr->im_intctl.ic_simrh);
91 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
92 simr[word] = ppc_cached_irq_mask[word];
95 static void m8260_mask_and_ack (unsigned int irq_nr)
97 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
99 volatile uint *simr, *sipnr;
101 bit = irq_to_siubit[irq_nr];
102 word = irq_to_siureg[irq_nr];
104 simr = &(immr->im_intctl.ic_simrh);
105 sipnr = &(immr->im_intctl.ic_sipnrh);
106 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
107 simr[word] = ppc_cached_irq_mask[word];
108 sipnr[word] = 1 << (31 - bit);
111 static int m8260_get_irq (struct pt_regs *regs)
113 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
117 /* For MPC8260, read the SIVEC register and shift the bits down
118 * to get the irq number. */
119 bits = immr->im_intctl.ic_sivec;
124 /* end of code ripped out of arch/powerpc/kernel/ppc8260_pic.c */
125 /****************************************************************************/
127 int interrupt_init_cpu (unsigned *decrementer_count)
129 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
131 *decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ;
133 /* Initialize the default interrupt mapping priorities */
134 immr->im_intctl.ic_sicr = 0;
135 immr->im_intctl.ic_siprr = 0x05309770;
136 immr->im_intctl.ic_scprrh = 0x05309770;
137 immr->im_intctl.ic_scprrl = 0x05309770;
139 /* disable all interrupts and clear all pending bits */
140 immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
141 immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
142 immr->im_intctl.ic_sipnrh = 0xffffffff;
143 immr->im_intctl.ic_sipnrl = 0xffffffff;
147 * ensure all external interrupt sources default to trigger on
148 * high-to-low transition (i.e. edge triggered active low)
150 immr->im_intctl.ic_siexr = -1;
156 /****************************************************************************/
159 * Handle external interrupts
161 void external_interrupt (struct pt_regs *regs)
165 irq = m8260_get_irq (regs);
167 m8260_mask_and_ack (irq);
169 enable_interrupts ();
171 if (irq_handlers[irq].handler != NULL)
172 (*irq_handlers[irq].handler) (irq_handlers[irq].arg);
174 printf ("\nBogus External Interrupt IRQ %d\n", irq);
176 * turn off the bogus interrupt, otherwise it
177 * might repeat forever
183 m8260_unmask_irq (irq);
186 /****************************************************************************/
189 * Install and free an interrupt handler.
193 irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
195 if (irq < 0 || irq >= NR_IRQS) {
196 printf ("irq_install_handler: bad irq number %d\n", irq);
200 if (irq_handlers[irq].handler != NULL)
201 printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
202 (ulong) handler, (ulong) irq_handlers[irq].handler);
204 irq_handlers[irq].handler = handler;
205 irq_handlers[irq].arg = arg;
207 m8260_unmask_irq (irq);
210 void irq_free_handler (int irq)
212 if (irq < 0 || irq >= NR_IRQS) {
213 printf ("irq_free_handler: bad irq number %d\n", irq);
217 m8260_mask_irq (irq);
219 irq_handlers[irq].handler = NULL;
220 irq_handlers[irq].arg = NULL;
223 /****************************************************************************/
225 void timer_interrupt_cpu (struct pt_regs *regs)
227 /* nothing to do here */
231 /****************************************************************************/
233 #if defined(CONFIG_CMD_IRQ)
235 /* ripped this out of ppc4xx/interrupts.c */
237 /*******************************************************************************
239 * irqinfo - print information about PCI devices
243 do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
247 re_enable = disable_interrupts ();
249 puts ("\nInterrupt-Information:\n"
250 "Nr Routine Arg Count\n");
252 for (irq = 0; irq < 32; irq++)
253 if (irq_handlers[irq].handler != NULL)
254 printf ("%02d %08lx %08lx %ld\n", irq,
255 (ulong) irq_handlers[irq].handler,
256 (ulong) irq_handlers[irq].arg,
257 irq_handlers[irq].count);
260 enable_interrupts ();