2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
7 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
8 * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
9 * Linux/PPC sources (m8260_tty.c had no copyright info in it).
13 * Minimal serial functions needed to use one of the SMC ports
14 * as serial console interface.
19 #include <asm/cpm_8260.h>
21 #include <linux/compiler.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #if defined(CONFIG_CONS_ON_SMC)
27 #if CONFIG_CONS_INDEX == 1 /* Console on SMC1 */
30 #define PROFF_SMC_BASE PROFF_SMC1_BASE
31 #define PROFF_SMC PROFF_SMC1
32 #define CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
33 #define CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
34 #define CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
35 #define CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
37 #elif CONFIG_CONS_INDEX == 2 /* Console on SMC2 */
40 #define PROFF_SMC_BASE PROFF_SMC2_BASE
41 #define PROFF_SMC PROFF_SMC2
42 #define CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
43 #define CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
44 #define CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
45 #define CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
49 #error "console not correctly defined"
53 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
54 #define CONFIG_SYS_SMC_RXBUFLEN 1
55 #define CONFIG_SYS_MAXIDLE 0
57 #if !defined(CONFIG_SYS_MAXIDLE)
58 #error "you must define CONFIG_SYS_MAXIDLE"
62 typedef volatile struct serialbuffer {
63 cbd_t rxbd; /* Rx BD */
64 cbd_t txbd; /* Tx BD */
65 uint rxindex; /* index for next character to read */
66 volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
67 volatile uchar txbuf; /* tx buffers */
70 /* map rs_table index to baud rate generator index */
71 static unsigned char brg_map[] = {
72 6, /* BRG7 for SMC1 */
73 7, /* BRG8 for SMC2 */
74 0, /* BRG1 for SCC1 */
75 1, /* BRG1 for SCC2 */
76 2, /* BRG1 for SCC3 */
77 3, /* BRG1 for SCC4 */
80 static int mpc8260_smc_serial_init(void)
82 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
84 volatile smc_uart_t *up;
85 volatile cpm8260_t *cp = &(im->im_cpm);
87 volatile serialbuffer_t *rtx;
89 /* initialize pointers to SMC */
91 sp = (smc_t *) &(im->im_smc[SMC_INDEX]);
92 im->im_dprambase16[PROFF_SMC_BASE / sizeof(u16)] = PROFF_SMC;
93 up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
95 /* Disable transmitter/receiver. */
96 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
98 /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
100 /* Allocate space for two buffer descriptors in the DP ram.
101 * damm: allocating space after the two buffers for rx/tx data
104 /* allocate size of struct serialbuffer with bd rx/tx,
105 * buffer rx/tx and rx index
107 dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16);
109 rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr];
111 /* Set the physical address of the host memory buffers in
112 * the buffer descriptors.
114 rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
115 rtx->rxbd.cbd_sc = 0;
117 rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
118 rtx->txbd.cbd_sc = 0;
120 /* Set up the uart parameters in the parameter ram. */
121 up->smc_rbase = dpaddr;
122 up->smc_tbase = dpaddr+sizeof(cbd_t);
123 up->smc_rfcr = CPMFCR_EB;
124 up->smc_tfcr = CPMFCR_EB;
129 /* Set UART mode, 8 bit, no parity, one stop.
130 * Enable receive and transmit.
132 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
134 /* Mask all interrupts and remove anything pending. */
138 /* put the SMC channel into NMSI (non multiplexd serial interface)
139 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
141 im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE;
143 /* Set up the baud rate generator. */
146 /* Make the first buffer the only buffer. */
147 rtx->txbd.cbd_sc |= BD_SC_WRAP;
148 rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
150 /* single/multi character receive. */
151 up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
152 up->smc_maxidl = CONFIG_SYS_MAXIDLE;
155 /* Initialize Tx/Rx parameters. */
157 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
160 cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK,
161 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
163 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
166 /* Enable transmitter/receiver. */
167 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
172 static void mpc8260_smc_serial_setbrg(void)
174 #if defined(CONFIG_CONS_USE_EXTC)
175 m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
176 CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
178 m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate);
182 static void mpc8260_smc_serial_putc(const char c)
184 volatile smc_uart_t *up;
185 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
186 volatile serialbuffer_t *rtx;
191 up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
193 rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
195 /* Wait for last character to go. */
196 while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY)
199 rtx->txbd.cbd_datlen = 1;
200 rtx->txbd.cbd_sc |= BD_SC_READY;
203 static int mpc8260_smc_serial_getc(void)
205 volatile smc_uart_t *up;
206 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
207 volatile serialbuffer_t *rtx;
210 up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
212 rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
214 /* Wait for character to show up. */
215 while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
218 /* the characters are read one by one,
219 * use the rxindex to know the next char to deliver
221 c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex);
224 /* check if all char are readout, then make prepare for next receive */
225 if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
227 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
232 static int mpc8260_smc_serial_tstc(void)
234 volatile smc_uart_t *up;
235 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
236 volatile serialbuffer_t *rtx;
238 up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
239 rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
241 return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
244 static struct serial_device mpc8260_smc_serial_drv = {
245 .name = "mpc8260_smc_uart",
246 .start = mpc8260_smc_serial_init,
248 .setbrg = mpc8260_smc_serial_setbrg,
249 .putc = mpc8260_smc_serial_putc,
250 .puts = default_serial_puts,
251 .getc = mpc8260_smc_serial_getc,
252 .tstc = mpc8260_smc_serial_tstc,
255 void mpc8260_smc_serial_initialize(void)
257 serial_register(&mpc8260_smc_serial_drv);
260 __weak struct serial_device *default_serial_console(void)
262 return &mpc8260_smc_serial_drv;
264 #endif /* CONFIG_CONS_ON_SMC */
266 #if defined(CONFIG_KGDB_ON_SMC)
268 #if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
269 #error Whoops! serial console and kgdb are on the same smc serial port
272 #if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SMC1 */
274 #define KGDB_SMC_INDEX 0
275 #define KGDB_PROFF_SMC_BASE PROFF_SMC1_BASE
276 #define KGDB_PROFF_SMC PROFF_SMC1
277 #define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
278 #define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
279 #define KGDB_CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
280 #define KGDB_CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
282 #elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SMC2 */
284 #define KGDB_SMC_INDEX 1
285 #define KGDB_PROFF_SMC_BASE PROFF_SMC2_BASE
286 #define KGDB_PROFF_SMC PROFF_SMC2
287 #define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
288 #define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
289 #define KGDB_CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
290 #define KGDB_CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
294 #error "console not correctly defined"
299 kgdb_serial_init (void)
301 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
303 volatile smc_uart_t *up;
304 volatile cbd_t *tbdf, *rbdf;
305 volatile cpm8260_t *cp = &(im->im_cpm);
306 uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
309 if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
310 ulong rate = simple_strtoul(s, &e, 10);
311 if (e > s && *e == '\0')
315 /* initialize pointers to SMC */
317 sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]);
318 im->im_dprambase16[KGDB_PROFF_SMC_BASE / sizeof(u16)] = KGDB_PROFF_SMC;
319 up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
321 /* Disable transmitter/receiver. */
322 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
324 /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
326 /* Allocate space for two buffer descriptors in the DP ram.
327 * damm: allocating space after the two buffers for rx/tx data
330 dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
332 /* Set the physical address of the host memory buffers in
333 * the buffer descriptors.
335 rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
336 rbdf->cbd_bufaddr = (uint) (rbdf+2);
339 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
342 /* Set up the uart parameters in the parameter ram. */
343 up->smc_rbase = dpaddr;
344 up->smc_tbase = dpaddr+sizeof(cbd_t);
345 up->smc_rfcr = CPMFCR_EB;
346 up->smc_tfcr = CPMFCR_EB;
351 /* Set UART mode, 8 bit, no parity, one stop.
352 * Enable receive and transmit.
354 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
356 /* Mask all interrupts and remove anything pending. */
360 /* put the SMC channel into NMSI (non multiplexd serial interface)
361 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
363 im->im_cpmux.cmx_smr =
364 (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE;
366 /* Set up the baud rate generator. */
367 #if defined(CONFIG_KGDB_USE_EXTC)
368 m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed,
369 CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
371 m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed);
374 /* Make the first buffer the only buffer. */
375 tbdf->cbd_sc |= BD_SC_WRAP;
376 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
378 /* Single character receive. */
382 /* Initialize Tx/Rx parameters. */
384 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
387 cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK,
388 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
390 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
393 /* Enable transmitter/receiver. */
394 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
396 printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
400 putDebugChar(const char c)
402 volatile cbd_t *tbdf;
404 volatile smc_uart_t *up;
405 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
410 up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
412 tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
414 /* Wait for last character to go. */
415 buf = (char *)tbdf->cbd_bufaddr;
416 while (tbdf->cbd_sc & BD_SC_READY)
420 tbdf->cbd_datlen = 1;
421 tbdf->cbd_sc |= BD_SC_READY;
425 putDebugStr (const char *s)
435 volatile cbd_t *rbdf;
436 volatile unsigned char *buf;
437 volatile smc_uart_t *up;
438 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
441 up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
443 rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
445 /* Wait for character to show up. */
446 buf = (unsigned char *)rbdf->cbd_bufaddr;
447 while (rbdf->cbd_sc & BD_SC_EMPTY)
450 rbdf->cbd_sc |= BD_SC_EMPTY;
456 kgdb_interruptible(int yes)
461 #endif /* CONFIG_KGDB_ON_SMC */