2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
12 #include <asm-offsets.h>
17 #include <ppc_asm.tmpl>
20 #include <asm/cache.h>
22 #include <asm/u-boot.h>
24 /* We don't want the MMU yet.
27 /* Floating Point enable, Machine Check and Recoverable Interr. */
29 #define MSR_KERNEL (MSR_FP|MSR_RI)
31 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
35 * Set up GOT: Global Offset Table
37 * Use r12 to access the GOT
40 GOT_ENTRY(_GOT2_TABLE_)
41 GOT_ENTRY(_FIXUP_TABLE_)
44 GOT_ENTRY(_start_of_vectors)
45 GOT_ENTRY(_end_of_vectors)
46 GOT_ENTRY(transfer_to_handler)
50 GOT_ENTRY(__bss_start)
51 #if defined(CONFIG_HYMOD)
52 GOT_ENTRY(environment)
57 * Version string - must be in data segment because MPC8260 uses the first
58 * 256 bytes for the Hard Reset Configuration Word table (see below).
59 * Similarly, can't have the U-Boot Magic Number as the first thing in
60 * the image - don't know how this will affect the image tools, but I guess
66 .ascii U_BOOT_VERSION_STRING, "\0"
69 * Hard Reset Configuration Word (HRCW) table
71 * The Hard Reset Configuration Word (HRCW) sets a number of useful things
72 * such as whether there is an external memory controller, whether the
73 * PowerPC core is disabled (i.e. only the communications processor is
74 * active, accessed by another CPU on the bus), whether using external
75 * arbitration, external bus mode, boot port size, core initial prefix,
76 * internal space base, boot memory space, etc.
78 * These things dictate where the processor begins execution, where the
79 * boot ROM appears in memory, the memory controller setup when access
80 * boot ROM, etc. The HRCW is *extremely* important.
82 * The HRCW is read from the bus during reset. One CPU on the bus will
83 * be a hard reset configuration master, any others will be hard reset
84 * configuration slaves. The master reads eight HRCWs from flash during
85 * reset - the first it uses for itself, the other 7 it communicates to
86 * up to 7 configuration slaves by some complicated mechanism, which is
87 * not really important here.
89 * The configuration master performs 32 successive reads starting at address
90 * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
91 * bits is read, and always from byte lane D[0-7] (so that port size of the
92 * boot device does not matter). The first four reads form the 32 bit HRCW
93 * for the master itself. The second four reads form the HRCW for the first
94 * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
95 * concatenating the four bytes, with the first read placed in byte 0 (the
96 * most significant byte), and so on with the fourth read placed in byte 3
97 * (the least significant byte).
99 #define _HRCW_TABLE_ENTRY(w) \
100 .fill 8,1,(((w)>>24)&0xff); \
101 .fill 8,1,(((w)>>16)&0xff); \
102 .fill 8,1,(((w)>> 8)&0xff); \
103 .fill 8,1,(((w) )&0xff)
107 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER)
108 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1)
109 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2)
110 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3)
111 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4)
112 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5)
113 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6)
114 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7)
116 * After configuration, a system reset exception is executed using the
117 * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
118 * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
119 * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
120 * of MSR[IP] is determined by the CIP field in the HRCW.
122 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
123 * This determines the location of the boot ROM (flash or EPROM) in the
124 * processor's address space at boot time. As long as the HRCW is set up
125 * so that we eventually end up executing the code below when the processor
126 * executes the reset exception, the actual values used should not matter.
128 * Once we have got here, the address mask in OR0 is cleared so that the
129 * bottom 32K of the boot ROM is effectively repeated all throughout the
130 * processor's address space, after which we can jump to the absolute
131 * address at which the boot ROM was linked at compile time, and proceed
132 * to initialise the memory controller without worrying if the rug will be
133 * pulled out from under us, so to speak (it will be fine as long as we
134 * configure BR0 with the same boot ROM link address).
136 . = EXC_OFF_SYS_RESET
140 #if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
141 lis r3, CONFIG_SYS_DEFAULT_IMMR@h
145 rlwinm r4, r4, 0, 8, 5
151 #endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
153 mfmsr r5 /* save msr contents */
155 #if defined(CONFIG_COGENT)
156 /* this is what the cogent EPROM does */
161 #endif /* CONFIG_COGENT */
163 #if defined(CONFIG_SYS_DEFAULT_IMMR)
164 lis r3, CONFIG_SYS_IMMR@h
165 ori r3, r3, CONFIG_SYS_IMMR@l
166 lis r4, CONFIG_SYS_DEFAULT_IMMR@h
168 #endif /* CONFIG_SYS_DEFAULT_IMMR */
170 /* Initialise the MPC8260 processor core */
171 /*--------------------------------------------------------------*/
175 #ifndef CONFIG_SYS_RAMBOOT
176 /* When booting from ROM (Flash or EPROM), clear the */
177 /* Address Mask in OR0 so ROM appears everywhere */
178 /*--------------------------------------------------------------*/
180 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
186 /* Calculate absolute address in FLASH and jump there */
187 /*--------------------------------------------------------------*/
189 lis r3, CONFIG_SYS_MONITOR_BASE@h
190 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
191 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
196 #endif /* CONFIG_SYS_RAMBOOT */
198 /* initialize some things that are hard to access from C */
199 /*--------------------------------------------------------------*/
201 lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */
202 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
203 li r0, 0 /* Make room for stack frame header and */
204 stwu r0, -4(r1) /* clear final stack frame so that */
205 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
207 /* let the C-code set up the rest */
209 /* Be careful to keep code relocatable ! */
210 /*--------------------------------------------------------------*/
212 GET_GOT /* initialize GOT access */
215 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
218 bl init_debug /* set up debugging stuff */
221 bl board_init_f /* run 1st part of board init code (in Flash)*/
223 /* NOTREACHED - board_init_f() does not return */
229 .globl _start_of_vectors
233 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
235 /* Data Storage exception. */
236 STD_EXCEPTION(0x300, DataStorage, UnknownException)
238 /* Instruction Storage exception. */
239 STD_EXCEPTION(0x400, InstStorage, UnknownException)
241 /* External Interrupt exception. */
242 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
244 /* Alignment exception. */
247 EXCEPTION_PROLOG(SRR0, SRR1)
252 addi r3,r1,STACK_FRAME_OVERHEAD
253 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
255 /* Program check exception */
258 EXCEPTION_PROLOG(SRR0, SRR1)
259 addi r3,r1,STACK_FRAME_OVERHEAD
260 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
263 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
265 /* I guess we could implement decrementer, and may have
266 * to someday for timekeeping.
268 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
270 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
271 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
272 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
273 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
275 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
276 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
278 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
279 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
280 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
284 * This exception occurs when the program counter matches the
285 * Instruction Address Breakpoint Register (IABR).
287 * I want the cpu to halt if this occurs so I can hunt around
288 * with the debugger and look at things.
290 * When DEBUG is defined, both machine check enable (in the MSR)
291 * and checkstop reset enable (in the reset mode register) are
292 * turned off and so a checkstop condition will result in the cpu
295 * I force the cpu into a checkstop condition by putting an illegal
296 * instruction here (at least this is the theory).
298 * well - that didnt work, so just do an infinite loop!
302 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
304 STD_EXCEPTION(0x1400, SMI, UnknownException)
306 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
307 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
308 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
309 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
310 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
311 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
312 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
313 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
314 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
315 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
316 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
317 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
318 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
319 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
320 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
321 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
322 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
323 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
324 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
325 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
326 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
327 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
328 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
329 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
330 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
331 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
332 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
335 .globl _end_of_vectors
341 * This code finishes saving the registers to the exception frame
342 * and jumps to the appropriate handler for the exception.
343 * Register r21 is pointer into trap frame, r1 has new stack pointer.
345 .globl transfer_to_handler
356 andi. r24,r23,0x3f00 /* get vector offset */
360 lwz r24,0(r23) /* virtual address of handler */
361 lwz r23,4(r23) /* where to go when done */
366 rfi /* jump to handler, enable MMU */
369 mfmsr r28 /* Disable interrupts */
373 SYNC /* Some chip revs need this... */
388 lwz r2,_NIP(r1) /* Restore environment */
398 #if defined(CONFIG_COGENT)
401 * This code initialises the MPC8260 processor core
402 * (conforms to PowerPC 603e spec)
405 .globl cogent_init_8260
408 /* Taken from page 14 of CMA282 manual */
409 /*--------------------------------------------------------------*/
411 lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h
412 lis r3, CONFIG_SYS_IMMR@h
413 stw r3, IM_IMMR@l(r4)
414 lwz r3, IM_IMMR@l(r4)
416 lis r3, CONFIG_SYS_SYPCR@h
417 ori r3, r3, CONFIG_SYS_SYPCR@l
418 stw r3, IM_SYPCR@l(r4)
419 lwz r3, IM_SYPCR@l(r4)
421 lis r3, CONFIG_SYS_SCCR@h
422 ori r3, r3, CONFIG_SYS_SCCR@l
423 stw r3, IM_SCCR@l(r4)
424 lwz r3, IM_SCCR@l(r4)
427 /* the rest of this was disassembled from the */
428 /* EPROM code that came with my CMA282 CPU module */
429 /*--------------------------------------------------------------*/
443 /*--------------------------------------------------------------*/
447 #endif /* CONFIG_COGENT */
450 * This code initialises the MPC8260 processor core
451 * (conforms to PowerPC 603e spec)
452 * Note: expects original MSR contents to be in r5.
455 .globl init_8260_core
458 /* Initialize machine status; enable machine check interrupt */
459 /*--------------------------------------------------------------*/
461 li r3, MSR_KERNEL /* Set ME and RI flags */
462 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
464 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
466 SYNC /* Some chip revs need this... */
469 mtspr SRR1, r3 /* Make SRR1 match MSR */
471 /* Initialise the SYPCR early, and reset the watchdog (if req) */
472 /*--------------------------------------------------------------*/
474 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
475 #if !defined(CONFIG_COGENT)
476 lis r4, CONFIG_SYS_SYPCR@h
477 ori r4, r4, CONFIG_SYS_SYPCR@l
478 stw r4, IM_SYPCR@l(r3)
479 #endif /* !CONFIG_COGENT */
480 #if defined(CONFIG_WATCHDOG)
481 li r4, 21868 /* = 0x556c */
482 sth r4, IM_SWSR@l(r3)
483 li r4, -21959 /* = 0xaa39 */
484 sth r4, IM_SWSR@l(r3)
485 #endif /* CONFIG_WATCHDOG */
487 /* Initialize the Hardware Implementation-dependent Registers */
488 /* HID0 also contains cache control */
489 /*--------------------------------------------------------------*/
491 lis r3, CONFIG_SYS_HID0_INIT@h
492 ori r3, r3, CONFIG_SYS_HID0_INIT@l
496 lis r3, CONFIG_SYS_HID0_FINAL@h
497 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
501 lis r3, CONFIG_SYS_HID2@h
502 ori r3, r3, CONFIG_SYS_HID2@l
505 /* clear all BAT's */
506 /*--------------------------------------------------------------*/
527 /* invalidate all tlb's */
529 /* From the 603e User Manual: "The 603e provides the ability to */
530 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
531 /* instruction invalidates the TLB entry indexed by the EA, and */
532 /* operates on both the instruction and data TLBs simultaneously*/
533 /* invalidating four TLB entries (both sets in each TLB). The */
534 /* index corresponds to bits 15-19 of the EA. To invalidate all */
535 /* entries within both TLBs, 32 tlbie instructions should be */
536 /* issued, incrementing this field by one each time." */
538 /* "Note that the tlbia instruction is not implemented on the */
541 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
542 /* incrementing by 0x1000 each time. The code below is sort of */
543 /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
545 /*--------------------------------------------------------------*/
556 /*--------------------------------------------------------------*/
563 * initialise things related to debugging.
565 * must be called after the global offset table (GOT) is initialised
566 * (GET_GOT) and after cpu_init_f() has executed.
572 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
574 /* Quick and dirty hack to enable the RAM and copy the */
575 /* vectors so that we can take exceptions. */
576 /*--------------------------------------------------------------*/
577 /* write Memory Refresh Prescaler */
578 li r4, CONFIG_SYS_MPTPR
579 sth r4, IM_MPTPR@l(r3)
580 /* write 60x Refresh Timer */
581 li r4, CONFIG_SYS_PSRT
582 stb r4, IM_PSRT@l(r3)
583 /* init the 60x SDRAM Mode Register */
584 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h
585 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l
586 stw r4, IM_PSDMR@l(r3)
587 /* write Precharge All Banks command */
588 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h
589 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l
590 stw r4, IM_PSDMR@l(r3)
592 /* write eight CBR Refresh commands */
593 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h
594 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l
595 stw r4, IM_PSDMR@l(r3)
604 /* write Mode Register Write command */
605 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h
606 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l
607 stw r4, IM_PSDMR@l(r3)
609 /* write Normal Operation command and enable Refresh */
610 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
611 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
612 stw r4, IM_PSDMR@l(r3)
614 /* RAM should now be operational */
616 #define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
620 lwz r3, GOT(_end_of_vectors)
621 rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */
622 lis r5, VEC_WRD_CNT@h
623 ori r5, r5, VEC_WRD_CNT@l
630 /* Load the Instruction Address Breakpoint Register (IABR). */
632 /* The address to load is stored in the first word of dual port */
633 /* ram and should be preserved while the power is on, so you */
634 /* can plug addresses into that location then reset the cpu and */
635 /* this code will load that address into the IABR after the */
638 /* When the program counter matches the contents of the IABR, */
639 /* an exception is generated (before the instruction at that */
640 /* location completes). The vector for this exception is 0x1300 */
641 /*--------------------------------------------------------------*/
642 lis r3, CONFIG_SYS_IMMR@h
646 /* Set the entire dual port RAM (where the initial stack */
647 /* resides) to a known value - makes it easier to see where */
648 /* the stack has been written */
649 /*--------------------------------------------------------------*/
650 lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h
651 ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l
652 li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4)
655 ori r4, r4, 0xdeadbeaf@l
661 /*--------------------------------------------------------------*/
668 * Note: requires that all cache bits in
669 * HID0 are in the low half word.
676 ori r4, r4, HID0_ILOCK
678 ori r4, r3, HID0_ICFI
680 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
682 mtspr HID0, r3 /* clears invalidate */
685 .globl icache_disable
689 ori r4, r4, HID0_ICE|HID0_ILOCK
691 ori r4, r3, HID0_ICFI
693 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
695 mtspr HID0, r3 /* clears invalidate */
701 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
709 ori r4, r4, HID0_DLOCK
713 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
715 mtspr HID0, r3 /* clears invalidate */
718 .globl dcache_disable
722 ori r4, r4, HID0_DCE|HID0_DLOCK
726 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
728 mtspr HID0, r3 /* clears invalidate */
734 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
742 /*------------------------------------------------------------------------------*/
745 * void relocate_code (addr_sp, gd, addr_moni)
747 * This "function" does not return, instead it continues in RAM
748 * after relocating the monitor code.
752 * r5 = length in bytes
757 mr r1, r3 /* Set new stack pointer */
758 mr r9, r4 /* Save copy of Global Data pointer */
759 mr r10, r5 /* Save copy of Destination Address */
762 mr r3, r5 /* Destination Address */
763 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
764 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
765 lwz r5, GOT(__init_end)
767 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
772 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
778 /* First our own GOT */
780 /* then the one used by the C code */
790 beq cr1,4f /* In place copy is not necessary */
791 beq 7f /* Protect against 0 count */
810 * Now flush the cache: note that we must start from a cache aligned
811 * address. Otherwise we might miss one cache line.
815 beq 7f /* Always flush prefetch queue in any case */
818 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
819 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
827 sync /* Wait for all dcbst to complete on bus */
828 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
829 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
837 7: sync /* Wait for all icbi to complete on bus */
841 * We are done. Do not return, instead branch to second part of board
842 * initialization, now running from RAM.
845 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
852 * Relocation Function, r12 point to got2+0x8000
854 * Adjust got2 pointers, no need to check for 0, this code
855 * already puts a few entries in the table.
857 li r0,__got2_entries@sectoff@l
858 la r3,GOT(_GOT2_TABLE_)
859 lwz r11,GOT(_GOT2_TABLE_)
871 * Now adjust the fixups and the pointers to the fixups
872 * in case we need to move ourselves again.
874 li r0,__fixup_entries@sectoff@l
875 lwz r3,GOT(_FIXUP_TABLE_)
891 * Now clear BSS segment
893 lwz r3,GOT(__bss_start)
894 #if defined(CONFIG_HYMOD)
896 * For HYMOD - the environment is the very last item in flash.
897 * The real .bss stops just before environment starts, so only
898 * clear up to that point.
900 * taken from mods for FADS board
902 lwz r4,GOT(environment)
904 lwz r4,GOT(__bss_end)
918 mr r3, r9 /* Global Data pointer */
919 mr r4, r10 /* Destination Address */
923 * Copy exception vector code to low memory
926 * r7: source address, r8: end address, r9: target address
930 mflr r4 /* save link register */
933 lwz r8, GOT(_end_of_vectors)
935 li r9, 0x100 /* reset vector always at 0x100 */
938 bgelr /* return if r7>=r8 - just in case */
948 * relocate `hdlr' and `int_return' entries
950 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
951 li r8, Alignment - _start + EXC_OFF_SYS_RESET
954 addi r7, r7, 0x100 /* next exception vector */
958 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
961 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
964 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
965 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
968 addi r7, r7, 0x100 /* next exception vector */
972 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
973 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
976 addi r7, r7, 0x100 /* next exception vector */
980 mfmsr r3 /* now that the vectors have */
981 lis r7, MSR_IP@h /* relocated into low memory */
982 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
983 andc r3, r3, r7 /* (if it was on) */
984 SYNC /* Some chip revs need this... */
988 mtlr r4 /* restore link register */