2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
37 #include <fsl_esdhc.h>
38 #ifdef CONFIG_BOOTCOUNT_LIMIT
39 #include <asm/immap_qe.h>
43 DECLARE_GLOBAL_DATA_PTR;
47 volatile immap_t *immr;
48 ulong clock = gd->cpu_clk;
54 const struct cpu_type {
57 } cpu_type_list [] = {
66 CPU_TYPE_ENTRY(8347_TBGA_),
67 CPU_TYPE_ENTRY(8347_PBGA_),
69 CPU_TYPE_ENTRY(8358_TBGA_),
70 CPU_TYPE_ENTRY(8358_PBGA_),
77 immr = (immap_t *)CONFIG_SYS_IMMR;
81 switch (pvr & 0xffff0000) {
99 printf("Unknown core, ");
102 spridr = immr->sysconf.spridr;
104 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
105 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
107 puts(cpu_type_list[i].name);
108 if (IS_E_PROCESSOR(spridr))
110 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
111 SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
112 REVID_MAJOR(spridr) >= 2)
114 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
115 REVID_MINOR(spridr));
119 if (i == ARRAY_SIZE(cpu_type_list))
120 printf("(SPRIDR %08x unknown), ", spridr);
122 printf(" at %s MHz, ", strmhz(buf, clock));
124 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
130 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
133 #ifndef MPC83xx_RESET
137 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
139 puts("Resetting the board.\n");
143 /* Interrupts and MMU off */
144 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
146 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
147 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
149 /* enable Reset Control Reg */
150 immap->reset.rpr = 0x52535445;
151 __asm__ __volatile__ ("sync");
152 __asm__ __volatile__ ("isync");
154 /* confirm Reset Control Reg is enabled */
155 while(!((immap->reset.rcer) & RCER_CRE));
159 /* perform reset, only one bit */
160 immap->reset.rcr = RCR_SWHR;
162 #else /* ! MPC83xx_RESET */
164 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
166 /* Interrupts and MMU off */
167 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
169 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
170 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
173 * Trying to execute the next instruction at a non-existing address
174 * should cause a machine check, resulting in reset
176 addr = CONFIG_SYS_RESET_ADDRESS;
178 ((void (*)(void)) addr) ();
179 #endif /* MPC83xx_RESET */
186 * Get timebase clock frequency (like cpu_clk in Hz)
189 unsigned long get_tbclk(void)
193 tbclk = (gd->bus_clk + 3L) / 4L;
199 #if defined(CONFIG_WATCHDOG)
200 void watchdog_reset (void)
202 int re_enable = disable_interrupts();
204 /* Reset the 83xx watchdog */
205 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
206 immr->wdt.swsrr = 0x556c;
207 immr->wdt.swsrr = 0xaa39;
210 enable_interrupts ();
215 * Initializes on-chip ethernet controllers.
216 * to override, implement board_eth_init()
218 int cpu_eth_init(bd_t *bis)
220 #if defined(CONFIG_UEC_ETH)
221 uec_standard_init(bis);
224 #if defined(CONFIG_TSEC_ENET)
225 tsec_standard_init(bis);
231 * Initializes on-chip MMC controllers.
232 * to override, implement board_mmc_init()
234 int cpu_mmc_init(bd_t *bis)
236 #ifdef CONFIG_FSL_ESDHC
237 return fsl_esdhc_mmc_init(bis);