1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * CPU specific code for the MPC83xx family.
9 * Derived from the MPC8260 and MPC85xx.
16 #include <asm/processor.h>
17 #include <linux/libfdt.h>
20 #include <fsl_esdhc.h>
21 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
22 #include <linux/immap_qe.h>
26 DECLARE_GLOBAL_DATA_PTR;
30 volatile immap_t *immr;
31 ulong clock = gd->cpu_clk;
38 const struct cpu_type {
41 } cpu_type_list [] = {
51 CPU_TYPE_ENTRY(8347_TBGA_),
52 CPU_TYPE_ENTRY(8347_PBGA_),
54 CPU_TYPE_ENTRY(8358_TBGA_),
55 CPU_TYPE_ENTRY(8358_PBGA_),
62 immr = (immap_t *)CONFIG_SYS_IMMR;
70 switch (pvr & 0xffff0000) {
88 printf("Unknown core, ");
91 spridr = immr->sysconf.spridr;
93 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
94 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
96 puts(cpu_type_list[i].name);
97 if (IS_E_PROCESSOR(spridr))
99 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
100 SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
101 REVID_MAJOR(spridr) >= 2)
103 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
104 REVID_MINOR(spridr));
108 if (i == ARRAY_SIZE(cpu_type_list))
109 printf("(SPRIDR %08x unknown), ", spridr);
111 printf(" at %s MHz, ", strmhz(buf, clock));
113 printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
119 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
122 #ifndef MPC83xx_RESET
126 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
128 puts("Resetting the board.\n");
132 /* Interrupts and MMU off */
133 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
135 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
136 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
138 /* enable Reset Control Reg */
139 immap->reset.rpr = 0x52535445;
140 __asm__ __volatile__ ("sync");
141 __asm__ __volatile__ ("isync");
143 /* confirm Reset Control Reg is enabled */
144 while(!((immap->reset.rcer) & RCER_CRE));
148 /* perform reset, only one bit */
149 immap->reset.rcr = RCR_SWHR;
151 #else /* ! MPC83xx_RESET */
153 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
155 /* Interrupts and MMU off */
156 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
158 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
159 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
162 * Trying to execute the next instruction at a non-existing address
163 * should cause a machine check, resulting in reset
165 addr = CONFIG_SYS_RESET_ADDRESS;
167 ((void (*)(void)) addr) ();
168 #endif /* MPC83xx_RESET */
175 * Get timebase clock frequency (like cpu_clk in Hz)
178 unsigned long get_tbclk(void)
180 return (gd->bus_clk + 3L) / 4L;
184 #if defined(CONFIG_WATCHDOG)
185 void watchdog_reset (void)
187 int re_enable = disable_interrupts();
189 /* Reset the 83xx watchdog */
190 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
191 immr->wdt.swsrr = 0x556c;
192 immr->wdt.swsrr = 0xaa39;
195 enable_interrupts ();
200 * Initializes on-chip ethernet controllers.
201 * to override, implement board_eth_init()
203 int cpu_eth_init(bd_t *bis)
205 #if defined(CONFIG_UEC_ETH)
206 uec_standard_init(bis);
209 #if defined(CONFIG_TSEC_ENET)
210 tsec_standard_init(bis);
216 * Initializes on-chip MMC controllers.
217 * to override, implement board_mmc_init()
219 int cpu_mmc_init(bd_t *bis)
221 #ifdef CONFIG_FSL_ESDHC
222 return fsl_esdhc_mmc_init(bis);