2 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #ifdef CONFIG_USB_EHCI_FSL
28 #include <usb/ehci-fsl.h>
31 DECLARE_GLOBAL_DATA_PTR;
34 extern qe_iop_conf_t qe_iop_conf_tab[];
35 extern void qe_config_iopin(u8 port, u8 pin, int dir,
36 int open_drain, int assign);
37 extern void qe_init(uint qe_base);
38 extern void qe_reset(void);
40 static void config_qe_ioports(void)
43 int dir, open_drain, assign;
46 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
47 port = qe_iop_conf_tab[i].port;
48 pin = qe_iop_conf_tab[i].pin;
49 dir = qe_iop_conf_tab[i].dir;
50 open_drain = qe_iop_conf_tab[i].open_drain;
51 assign = qe_iop_conf_tab[i].assign;
52 qe_config_iopin(port, pin, dir, open_drain, assign);
58 * Breathe some life into the CPU...
60 * Set up the memory map,
61 * initialize a bunch of registers,
62 * initialize the UPM's
64 void cpu_init_f (volatile immap_t * im)
67 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
70 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
73 #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
76 #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
81 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
82 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
84 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
85 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
87 #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
88 (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
90 #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
91 (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
95 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
98 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
101 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
104 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
109 #ifdef CONFIG_SYS_SPCR_OPT
110 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
112 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
113 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
115 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
116 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
118 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
119 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
123 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
126 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
129 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
132 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
135 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
138 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
141 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
144 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
147 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
150 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
153 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
156 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
161 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
162 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
164 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
165 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
167 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
168 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
170 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
171 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
173 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
174 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
176 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
177 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
179 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
180 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
182 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
183 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
185 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
186 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
188 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
189 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
191 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
192 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
194 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
195 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
199 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
202 #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
205 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
210 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
211 CONFIG_SYS_LCRR_DBYP |
213 #ifdef CONFIG_SYS_LCRR_EADC
214 CONFIG_SYS_LCRR_EADC |
216 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
217 CONFIG_SYS_LCRR_CLKDIV |
221 /* Pointer is writable since we allocated a register for it */
222 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
224 /* Clear initial global data */
225 memset ((void *) gd, 0, sizeof (gd_t));
227 /* system performance tweaking */
228 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
230 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
232 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
234 /* RSR - Reset Status Register - clear all status (4.6.1.3) */
235 gd->reset_status = __raw_readl(&im->reset.rsr);
236 __raw_writel(~(RSR_RES), &im->reset.rsr);
238 /* AER - Arbiter Event Register - store status */
239 gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
240 gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
243 * RMR - Reset Mode Register
244 * contains checkstop reset enable (4.6.1.4)
246 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
248 /* LCRR - Clock Ratio Register (10.3.1.16)
249 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
251 clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
252 __raw_readl(&im->im_lbc.lcrr);
255 /* Enable Time Base & Decrementer ( so we will have udelay() )*/
256 setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
258 /* System General Purpose Register */
259 #ifdef CONFIG_SYS_SICRH
260 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
261 /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
262 __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
265 __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
268 #ifdef CONFIG_SYS_SICRL
269 __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
271 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
272 __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
274 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
275 __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
279 /* Config QE ioports */
282 /* Set up preliminary BR/OR regs */
283 init_early_memctl_regs();
285 /* Local Access window setup */
286 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
287 im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
288 im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
290 #error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
293 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
294 im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
295 im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
297 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
298 im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
299 im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
301 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
302 im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
303 im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
305 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
306 im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
307 im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
309 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
310 im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
311 im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
313 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
314 im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
315 im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
317 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
318 im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
319 im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
321 #ifdef CONFIG_SYS_GPIO1_PRELIM
322 im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
323 im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
325 #ifdef CONFIG_SYS_GPIO2_PRELIM
326 im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
327 im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
329 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
331 struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
333 /* Configure interface. */
334 setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
336 /* Wait for clock to stabilize */
338 temp = __raw_readl(&ehci->control);
340 } while (!(temp & PHY_CLK_VALID));
344 int cpu_init_r (void)
347 uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
356 * Print out the bus arbiter event
358 #if defined(CONFIG_DISPLAY_AER_FULL)
359 static int print_83xx_arb_event(int force)
361 static char* event[] = {
364 "Address Only Transfer Type",
365 "External Control Word Transfer Type",
366 "Reserved Transfer Type",
371 static char* master[] = {
372 "e300 Core Data Transaction",
374 "e300 Core Instruction Fetch",
381 "I2C Boot Sequencer",
405 static char *transfer[] = {
406 "Address-only, Clean Block",
407 "Address-only, lwarx reservation set",
408 "Single-beat or Burst write",
410 "Address-only, Flush Block",
414 "Address-only, sync",
415 "Address-only, tlbsync",
416 "Single-beat or Burst read",
417 "Single-beat or Burst read",
418 "Address-only, Kill Block",
419 "Address-only, icbi",
422 "Address-only, eieio",
426 "ecowx - Illegal single-beat write",
430 "Address-only, TLB Invalidate",
432 "Single-beat or Burst read",
434 "eciwx - Illegal single-beat read",
440 int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
441 >> AEATR_EVENT_SHIFT;
442 int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
443 >> AEATR_MSTR_ID_SHIFT;
444 int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
446 int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
447 >> AEATR_TSIZE_SHIFT;
448 int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
449 >> AEATR_TTYPE_SHIFT;
451 if (!force && !gd->arbiter_event_address)
454 puts("Arbiter Event Status:\n");
455 printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
456 printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
457 printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
458 printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
459 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
460 printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
462 return gd->arbiter_event_address;
465 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
467 static int print_83xx_arb_event(int force)
469 if (!force && !gd->arbiter_event_address)
472 printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
473 gd->arbiter_event_attributes, gd->arbiter_event_address);
475 return gd->arbiter_event_address;
477 #endif /* CONFIG_DISPLAY_AER_xxxx */
480 * Figure out the cause of the reset
482 int prt_83xx_rsr(void)
489 RSR_SWSR, "Software Soft"}, {
490 RSR_SWHR, "Software Hard"}, {
491 RSR_JSRS, "JTAG Soft"}, {
492 RSR_CSHR, "Check Stop"}, {
493 RSR_SWRS, "Software Watchdog"}, {
494 RSR_BMRS, "Bus Monitor"}, {
495 RSR_SRS, "External/Internal Soft"}, {
496 RSR_HRS, "External/Internal Hard"}
498 static int n = sizeof bits / sizeof bits[0];
499 ulong rsr = gd->reset_status;
503 puts("Reset Status:");
506 for (i = 0; i < n; i++)
507 if (rsr & bits[i].mask) {
508 printf("%s%s", sep, bits[i].desc);
513 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
514 print_83xx_arb_event(rsr & RSR_BMRS);