2 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #ifdef CONFIG_USB_EHCI_FSL
12 #include <usb/ehci-ci.h>
15 DECLARE_GLOBAL_DATA_PTR;
18 extern qe_iop_conf_t qe_iop_conf_tab[];
19 extern void qe_config_iopin(u8 port, u8 pin, int dir,
20 int open_drain, int assign);
21 extern void qe_init(uint qe_base);
22 extern void qe_reset(void);
24 static void config_qe_ioports(void)
27 int dir, open_drain, assign;
30 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
31 port = qe_iop_conf_tab[i].port;
32 pin = qe_iop_conf_tab[i].pin;
33 dir = qe_iop_conf_tab[i].dir;
34 open_drain = qe_iop_conf_tab[i].open_drain;
35 assign = qe_iop_conf_tab[i].assign;
36 qe_config_iopin(port, pin, dir, open_drain, assign);
42 * Breathe some life into the CPU...
44 * Set up the memory map,
45 * initialize a bunch of registers,
46 * initialize the UPM's
48 void cpu_init_f (volatile immap_t * im)
51 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
54 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
57 #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
60 #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
65 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
66 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
68 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
69 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
71 #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
72 (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
74 #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
75 (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
79 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
82 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
85 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
88 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
93 #ifdef CONFIG_SYS_SPCR_OPT
94 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
96 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
97 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
99 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
100 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
102 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
103 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
107 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
110 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
113 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
116 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
119 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
122 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
125 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
128 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
131 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
134 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
137 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
140 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
145 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
146 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
148 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
149 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
151 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
152 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
154 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
155 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
157 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
158 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
160 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
161 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
163 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
164 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
166 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
167 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
169 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
170 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
172 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
173 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
175 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
176 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
178 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
179 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
183 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
186 #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
189 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
194 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
195 CONFIG_SYS_LCRR_DBYP |
197 #ifdef CONFIG_SYS_LCRR_EADC
198 CONFIG_SYS_LCRR_EADC |
200 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
201 CONFIG_SYS_LCRR_CLKDIV |
205 /* Pointer is writable since we allocated a register for it */
206 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
208 /* global data region was cleared in start.S */
210 /* system performance tweaking */
211 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
213 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
215 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
217 /* RSR - Reset Status Register - clear all status (4.6.1.3) */
218 gd->arch.reset_status = __raw_readl(&im->reset.rsr);
219 __raw_writel(~(RSR_RES), &im->reset.rsr);
221 /* AER - Arbiter Event Register - store status */
222 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
223 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
226 * RMR - Reset Mode Register
227 * contains checkstop reset enable (4.6.1.4)
229 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
231 /* LCRR - Clock Ratio Register (10.3.1.16)
232 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
234 clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
235 __raw_readl(&im->im_lbc.lcrr);
238 /* Enable Time Base & Decrementer ( so we will have udelay() )*/
239 setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
241 /* System General Purpose Register */
242 #ifdef CONFIG_SYS_SICRH
243 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
244 /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
245 __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
248 __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
251 #ifdef CONFIG_SYS_SICRL
252 __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
254 #ifdef CONFIG_SYS_GPR1
255 __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
257 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
258 __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
260 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
261 __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
265 /* Config QE ioports */
268 /* Set up preliminary BR/OR regs */
269 init_early_memctl_regs();
271 /* Local Access window setup */
272 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
273 im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
274 im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
276 #error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
279 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
280 im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
281 im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
283 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
284 im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
285 im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
287 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
288 im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
289 im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
291 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
292 im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
293 im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
295 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
296 im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
297 im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
299 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
300 im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
301 im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
303 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
304 im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
305 im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
307 #ifdef CONFIG_SYS_GPIO1_PRELIM
308 im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
309 im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
311 #ifdef CONFIG_SYS_GPIO2_PRELIM
312 im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
313 im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
315 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
317 struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
319 /* Configure interface. */
320 setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
322 /* Wait for clock to stabilize */
324 temp = __raw_readl(&ehci->control);
326 } while (!(temp & PHY_CLK_VALID));
330 int cpu_init_r (void)
333 uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
342 * Print out the bus arbiter event
344 #if defined(CONFIG_DISPLAY_AER_FULL)
345 static int print_83xx_arb_event(int force)
347 static char* event[] = {
350 "Address Only Transfer Type",
351 "External Control Word Transfer Type",
352 "Reserved Transfer Type",
357 static char* master[] = {
358 "e300 Core Data Transaction",
360 "e300 Core Instruction Fetch",
367 "I2C Boot Sequencer",
391 static char *transfer[] = {
392 "Address-only, Clean Block",
393 "Address-only, lwarx reservation set",
394 "Single-beat or Burst write",
396 "Address-only, Flush Block",
400 "Address-only, sync",
401 "Address-only, tlbsync",
402 "Single-beat or Burst read",
403 "Single-beat or Burst read",
404 "Address-only, Kill Block",
405 "Address-only, icbi",
408 "Address-only, eieio",
412 "ecowx - Illegal single-beat write",
416 "Address-only, TLB Invalidate",
418 "Single-beat or Burst read",
420 "eciwx - Illegal single-beat read",
426 int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
427 >> AEATR_EVENT_SHIFT;
428 int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
429 >> AEATR_MSTR_ID_SHIFT;
430 int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
432 int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
433 >> AEATR_TSIZE_SHIFT;
434 int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
435 >> AEATR_TTYPE_SHIFT;
437 if (!force && !gd->arch.arbiter_event_address)
440 puts("Arbiter Event Status:\n");
441 printf(" Event Address: 0x%08lX\n",
442 gd->arch.arbiter_event_address);
443 printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
444 printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
445 printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
446 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
447 printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
449 return gd->arch.arbiter_event_address;
452 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
454 static int print_83xx_arb_event(int force)
456 if (!force && !gd->arch.arbiter_event_address)
459 printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
460 gd->arch.arbiter_event_attributes,
461 gd->arch.arbiter_event_address);
463 return gd->arch.arbiter_event_address;
465 #endif /* CONFIG_DISPLAY_AER_xxxx */
468 * Figure out the cause of the reset
470 int prt_83xx_rsr(void)
477 RSR_SWSR, "Software Soft"}, {
478 RSR_SWHR, "Software Hard"}, {
479 RSR_JSRS, "JTAG Soft"}, {
480 RSR_CSHR, "Check Stop"}, {
481 RSR_SWRS, "Software Watchdog"}, {
482 RSR_BMRS, "Bus Monitor"}, {
483 RSR_SRS, "External/Internal Soft"}, {
484 RSR_HRS, "External/Internal Hard"}
486 static int n = ARRAY_SIZE(bits);
487 ulong rsr = gd->arch.reset_status;
491 puts("Reset Status:");
494 for (i = 0; i < n; i++)
495 if (rsr & bits[i].mask) {
496 printf("%s%s", sep, bits[i].desc);
501 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
502 print_83xx_arb_event(rsr & RSR_BMRS);