git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc83xx/fdt.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <libfdt.h>
  12 #include <fdt_support.h>
  13 #include <asm/processor.h>
  14
  15 extern void ft_qe_setup(void *blob);
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #if defined(CONFIG_BOOTCOUNT_LIMIT) && \
  20         (defined(CONFIG_QE))
  21 #include <asm/immap_qe.h>
  22
  23 void fdt_fixup_muram (void *blob)
  24 {
  25         ulong data[2];
  26
  27         data[0] = 0;
  28         data[1] = QE_MURAM_SIZE - 2 * sizeof(unsigned long);
  29         do_fixup_by_compat(blob, "fsl,qe-muram-data", "reg",
  30                         data, sizeof (data), 0);
  31 }
  32 #endif
  33
  34 void ft_cpu_setup(void *blob, bd_t *bd)
  35 {
  36         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  37         int spridr = immr->sysconf.spridr;
  38
  39         /*
  40          * delete crypto node if not on an E-processor
  41          * initial revisions of the MPC834xE/6xE have the original SEC 2.0.
  42          * EA revisions got the SEC uprevved to 2.4 but since the default device
  43          * tree contains SEC 2.0 properties we uprev them here.
  44          */
  45         if (!IS_E_PROCESSOR(spridr))
  46                 fdt_fixup_crypto_node(blob, 0);
  47         else if (IS_E_PROCESSOR(spridr) &&
  48                  (SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
  49                   SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
  50                  REVID_MAJOR(spridr) >= 2)
  51                 fdt_fixup_crypto_node(blob, 0x0204);
  52
  53 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
  54     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
  55     defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
  56         fdt_fixup_ethernet(blob);
  57 #ifdef CONFIG_MPC8313
  58         /*
  59         * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
  60         * h/w (see AN3545).  The base device tree in use has rev. 1 ID numbers,
  61         * so if on Rev. 2 (and higher) h/w, we fix them up here
  62         */
  63         if (REVID_MAJOR(immr->sysconf.spridr) >= 2) {
  64                 int nodeoffset, path;
  65                 const char *prop;
  66
  67                 nodeoffset = fdt_path_offset(blob, "/aliases");
  68                 if (nodeoffset >= 0) {
  69 #if defined(CONFIG_HAS_ETH0)
  70                         prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
  71                         if (prop) {
  72                                 u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
  73
  74                                 path = fdt_path_offset(blob, prop);
  75                                 prop = fdt_getprop(blob, path, "interrupts",
  76                                                    NULL);
  77                                 if (prop)
  78                                         fdt_setprop(blob, path, "interrupts",
  79                                                     &tmp, sizeof(tmp));
  80                         }
  81 #endif
  82 #if defined(CONFIG_HAS_ETH1)
  83                         prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
  84                         if (prop) {
  85                                 u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
  86
  87                                 path = fdt_path_offset(blob, prop);
  88                                 prop = fdt_getprop(blob, path, "interrupts",
  89                                                    NULL);
  90                                 if (prop)
  91                                         fdt_setprop(blob, path, "interrupts",
  92                                                     &tmp, sizeof(tmp));
  93                         }
  94 #endif
  95                 }
  96         }
  97 #endif
  98 #endif
  99
 100         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 101                 "timebase-frequency", (bd->bi_busfreq / 4), 1);
 102         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 103                 "bus-frequency", bd->bi_busfreq, 1);
 104         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 105                 "clock-frequency", gd->arch.core_clk, 1);
 106         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 107                 "bus-frequency", bd->bi_busfreq, 1);
 108         do_fixup_by_compat_u32(blob, "fsl,soc",
 109                 "bus-frequency", bd->bi_busfreq, 1);
 110         do_fixup_by_compat_u32(blob, "fsl,soc",
 111                 "clock-frequency", bd->bi_busfreq, 1);
 112         do_fixup_by_compat_u32(blob, "fsl,immr",
 113                 "bus-frequency", bd->bi_busfreq, 1);
 114         do_fixup_by_compat_u32(blob, "fsl,immr",
 115                 "clock-frequency", bd->bi_busfreq, 1);
 116 #ifdef CONFIG_QE
 117         ft_qe_setup(blob);
 118 #endif
 119
 120 #ifdef CONFIG_SYS_NS16550
 121         do_fixup_by_compat_u32(blob, "ns16550",
 122                 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 123 #endif
 124
 125         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 126
 127 #if defined(CONFIG_BOOTCOUNT_LIMIT)
 128         fdt_fixup_muram (blob);
 129 #endif
 130 }