2 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
3 * Copyright (C) 2008-2009 MontaVista Software, Inc.
5 * Authors: Tony Li <tony.li@freescale.com>
6 * Anton Vorontsov <avorontsov@ru.mvista.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 DECLARE_GLOBAL_DATA_PTR;
31 #define PCIE_MAX_BUSES 2
36 } mpc83xx_pcie_cfg_space[] = {
38 .base = CONFIG_SYS_PCIE1_CFG_BASE,
39 .size = CONFIG_SYS_PCIE1_CFG_SIZE,
41 #if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
43 .base = CONFIG_SYS_PCIE2_CFG_BASE,
44 .size = CONFIG_SYS_PCIE2_CFG_SIZE,
49 #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
51 static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
53 int bus = PCI_BUS(dev) - hose->first_busno;
54 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
55 pex83xx_t *pex = &immr->pciexp[bus];
56 struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
57 u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
58 u32 dev_base = bus << 24 | devfn << 16;
60 if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
63 * Workaround for the HW bug: for Type 0 configure transactions the
64 * PCI-E controller does not check the device number bits and just
65 * assumes that the device number bits are 0.
70 out_le32(&out_win->tarl, dev_base);
74 #define cfg_read(val, addr, type, op) \
75 do { *val = op((type)(addr)); } while (0)
76 #define cfg_write(val, addr, type, op) \
77 do { op((type *)(addr), (val)); } while (0)
79 #define cfg_read_err(val) do { *val = -1; } while (0)
80 #define cfg_write_err(val) do { } while (0)
82 #define PCIE_OP(rw, size, type, op) \
83 static int pcie_##rw##_config_##size(struct pci_controller *hose, \
84 pci_dev_t dev, int offset, \
89 ret = mpc83xx_pcie_remap_cfg(hose, dev); \
91 cfg_##rw##_err(val); \
94 cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
98 PCIE_OP(read, byte, u8 *, in_8)
99 PCIE_OP(read, word, u16 *, in_le16)
100 PCIE_OP(read, dword, u32 *, in_le32)
101 PCIE_OP(write, byte, u8, out_8)
102 PCIE_OP(write, word, u16, out_le16)
103 PCIE_OP(write, dword, u32, out_le32)
105 static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
108 extern void disable_addr_trans(void); /* start.S */
109 static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
110 struct pci_controller *hose = &pcie_hose[bus];
114 * There are no spare BATs to remap all PCI-E windows for U-Boot, so
115 * disable translations. In general, this is not great solution, and
116 * that's why we don't register PCI-E hoses by default.
118 disable_addr_trans();
120 for (i = 0; i < 2; i++, reg++) {
124 hose->regions[i] = *reg;
125 hose->region_count++;
128 i = hose->region_count++;
129 hose->regions[i].bus_start = 0;
130 hose->regions[i].phys_start = 0;
131 hose->regions[i].size = gd->ram_size;
132 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
134 i = hose->region_count++;
135 hose->regions[i].bus_start = CONFIG_SYS_IMMR;
136 hose->regions[i].phys_start = CONFIG_SYS_IMMR;
137 hose->regions[i].size = 0x100000;
138 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
140 hose->first_busno = pci_last_busno() + 1;
141 hose->last_busno = 0xff;
143 hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
146 pcie_read_config_byte,
147 pcie_read_config_word,
148 pcie_read_config_dword,
149 pcie_write_config_byte,
150 pcie_write_config_word,
151 pcie_write_config_dword);
154 hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
156 pci_register_hose(hose);
158 #ifdef CONFIG_PCI_SCAN_SHOW
159 printf("PCI: Bus Dev VenId DevId Class Int\n");
164 hose->last_busno = pci_hose_scan(hose);
169 static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
172 #endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
174 static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
176 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
177 pex83xx_t *pex = &immr->pciexp[bus];
178 struct pex_outbound_window *out_win;
179 struct pex_inbound_window *in_win;
187 /* Enable pex csb bridge inbound & outbound transactions */
188 out_le32(&pex->bridge.pex_csb_ctrl,
189 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
190 PEX_CSB_CTRL_IBPIOE);
192 /* Enable bridge outbound */
193 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
194 PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
195 PEX_CSB_OBCTRL_CFGWE);
197 out_win = &pex->bridge.pex_outbound_win[0];
198 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
199 mpc83xx_pcie_cfg_space[bus].size);
200 out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
201 out_le32(&out_win->tarl, 0);
202 out_le32(&out_win->tarh, 0);
204 for (i = 0; i < 2; i++, reg++) {
210 out_win = &pex->bridge.pex_outbound_win[i + 1];
211 out_le32(&out_win->bar, reg->phys_start);
212 out_le32(&out_win->tarl, reg->bus_start);
213 out_le32(&out_win->tarh, 0);
214 ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE);
215 if (reg->flags & PCI_REGION_IO)
216 ar |= PEX_OWAR_TYPE_IO;
218 ar |= PEX_OWAR_TYPE_MEM;
219 out_le32(&out_win->ar, ar);
222 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
224 ram_sz = gd->ram_size;
229 in_win = &pex->bridge.pex_inbound_win[i];
230 out_le32(&in_win->barl, barl);
231 out_le32(&in_win->barh, 0x0);
232 out_le32(&in_win->tar, tar);
233 if (ram_sz >= 0x10000000) {
234 /* The maxium windows size is 256M */
235 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
236 PEX_IWAR_TYPE_PF | 0x0FFFF000);
239 ram_sz -= 0x10000000;
241 /* The UM is not clear here.
242 * So, round up to even Mb boundary */
244 ram_sz = ram_sz >> (20 +
245 ((ram_sz & 0xFFFFF) ? 1 : 0));
248 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
249 PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
255 in_win = &pex->bridge.pex_inbound_win[i];
256 out_le32(&in_win->barl, CONFIG_SYS_IMMR);
257 out_le32(&in_win->barh, 0);
258 out_le32(&in_win->tar, CONFIG_SYS_IMMR);
259 out_le32(&in_win->ar, PEX_IWAR_EN |
260 PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
262 /* Enable the host virtual INTX interrupts */
263 out_le32(&pex->bridge.pex_int_axi_misc_enb,
264 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
266 /* Hose configure header is memory-mapped */
267 hose_cfg_base = (void *)pex;
270 /* Configure the PCIE controller core clock ratio */
271 out_le32(hose_cfg_base + PEX_GCLK_RATIO,
272 (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
276 /* Do Type 1 bridge configuration */
277 out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
278 out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
279 out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
282 * Write to Command register
284 reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
285 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
286 PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
287 out_le16(hose_cfg_base + PCI_COMMAND, reg16);
290 * Clear non-reserved bits in status register.
292 out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
293 out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
294 out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
296 printf("PCIE%d: ", bus);
298 reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
299 if (reg16 >= PCI_LTSSM_L0)
304 mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
308 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
309 * must have been set to cover all of the requested regions.
311 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
316 * Release PCI RST Output signal.
317 * Power on to RST high must be at least 100 ms as per PCI spec.
318 * On warm boots only 1 ms is required, but we play it safe.
322 if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
323 printf("Second PCIE host contoller not configured!\n");
324 num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
327 for (i = 0; i < num_buses; i++)
328 mpc83xx_pcie_init_bus(i, reg[i]);