2 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
8 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
36 #include <spd_sdram.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 void board_add_ram_info(int use_default)
42 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
43 volatile ddr83xx_t *ddr = &immap->ddr;
46 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
47 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
49 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
50 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
52 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
55 puts(", unknown width");
57 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
63 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
68 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
70 #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
72 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
76 #ifdef CONFIG_SPD_EEPROM
77 #ifndef CONFIG_SYS_READ_SPD
78 #define CONFIG_SYS_READ_SPD i2c_read
80 #ifndef SPD_EEPROM_OFFSET
81 #define SPD_EEPROM_OFFSET 0
83 #ifndef SPD_EEPROM_ADDR_LEN
84 #define SPD_EEPROM_ADDR_LEN 1
88 * Convert picoseconds into clock cycles (rounding up if needed).
91 picos_to_clk(int picos)
93 unsigned int mem_bus_clk;
96 mem_bus_clk = gd->mem_clk >> 1;
97 clks = picos / (1000000000 / (mem_bus_clk / 1000));
98 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
104 unsigned int banksize(unsigned char row_dens)
106 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
109 int read_spd(uint addr)
116 static void spd_debug(spd_eeprom_t *spd)
118 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
119 printf ("SPD size: %d\n", spd->info_size);
120 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
121 printf ("Memory type: %d\n", spd->mem_type);
122 printf ("Row addr: %d\n", spd->nrow_addr);
123 printf ("Column addr: %d\n", spd->ncol_addr);
124 printf ("# of rows: %d\n", spd->nrows);
125 printf ("Row density: %d\n", spd->row_dens);
126 printf ("# of banks: %d\n", spd->nbanks);
127 printf ("Data width: %d\n",
128 256 * spd->dataw_msb + spd->dataw_lsb);
129 printf ("Chip width: %d\n", spd->primw);
130 printf ("Refresh rate: %02X\n", spd->refresh);
131 printf ("CAS latencies: %02X\n", spd->cas_lat);
132 printf ("Write latencies: %02X\n", spd->write_lat);
133 printf ("tRP: %d\n", spd->trp);
134 printf ("tRCD: %d\n", spd->trcd);
137 #endif /* SPD_DEBUG */
141 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
142 volatile ddr83xx_t *ddr = &immap->ddr;
143 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
145 unsigned int n_ranks;
146 unsigned int odt_rd_cfg, odt_wr_cfg;
147 unsigned char twr_clk, twtr_clk;
148 unsigned int sdram_type;
149 unsigned int memsize;
150 unsigned int law_size;
151 unsigned char caslat, caslat_ctrl;
152 unsigned int trfc, trfc_clk, trfc_low;
153 unsigned int trcd_clk, trtp_clk;
154 unsigned char cke_min_clk;
155 unsigned char add_lat, wr_lat;
156 unsigned char wr_data_delay;
157 unsigned char four_act;
159 unsigned char burstlen;
160 unsigned char odt_cfg, mode_odt_enable;
161 unsigned int max_bus_clk;
162 unsigned int max_data_rate, effective_data_rate;
163 unsigned int ddrc_clk;
164 unsigned int refresh_clk;
165 unsigned int sdram_cfg;
166 unsigned int ddrc_ecc_enable;
167 unsigned int pvr = get_pvr();
170 * First disable the memory controller (could be enabled
173 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
177 /* Read SPD parameters with I2C */
178 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
179 SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
183 /* Check the memory type */
184 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
185 debug("DDR: Module mem type is %02X\n", spd.mem_type);
189 /* Check the number of physical bank */
190 if (spd.mem_type == SPD_MEMTYPE_DDR) {
193 n_ranks = (spd.nrows & 0x7) + 1;
197 printf("DDR: The number of physical bank is %02X\n", n_ranks);
201 /* Check if the number of row of the module is in the range of DDRC */
202 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
203 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
208 /* Check if the number of col of the module is in the range of DDRC */
209 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
210 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
215 #ifdef CONFIG_SYS_DDRCDR_VALUE
217 * Adjust DDR II IO voltage biasing. It just makes it work.
219 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
220 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
226 * ODT configuration recommendation from DDR Controller Chapter.
228 odt_rd_cfg = 0; /* Never assert ODT */
229 odt_wr_cfg = 0; /* Never assert ODT */
230 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
231 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
234 /* Setup DDR chip select register */
235 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
236 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
237 ddr->cs_config[0] = ( 1 << 31
240 | ((spd.nbanks == 8 ? 1 : 0) << 14)
241 | ((spd.nrow_addr - 12) << 8)
242 | (spd.ncol_addr - 8) );
244 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
245 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
248 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
249 | ((banksize(spd.row_dens) >> 23) - 1) );
250 ddr->cs_config[1] = ( 1<<31
253 | ((spd.nbanks == 8 ? 1 : 0) << 14)
254 | ((spd.nrow_addr - 12) << 8)
255 | (spd.ncol_addr - 8) );
256 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
257 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
261 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
262 ddr->cs_config[2] = ( 1 << 31
265 | ((spd.nbanks == 8 ? 1 : 0) << 14)
266 | ((spd.nrow_addr - 12) << 8)
267 | (spd.ncol_addr - 8) );
269 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
270 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
273 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
274 | ((banksize(spd.row_dens) >> 23) - 1) );
275 ddr->cs_config[3] = ( 1<<31
278 | ((spd.nbanks == 8 ? 1 : 0) << 14)
279 | ((spd.nrow_addr - 12) << 8)
280 | (spd.ncol_addr - 8) );
281 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
282 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
287 * Figure out memory size in Megabytes.
289 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
292 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
294 law_size = 19 + __ilog2(memsize);
297 * Set up LAWBAR for all of DDR.
299 ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
300 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
301 debug("DDR:bar=0x%08x\n", ecm->bar);
302 debug("DDR:ar=0x%08x\n", ecm->ar);
305 * Find the largest CAS by locating the highest 1 bit
306 * in the spd.cas_lat field. Translate it to a DDR
307 * controller field value:
309 * CAS Lat DDR I DDR II Ctrl
310 * Clocks SPD Bit SPD Bit Value
311 * ------- ------- ------- -----
322 caslat = __ilog2(spd.cas_lat);
323 if ((spd.mem_type == SPD_MEMTYPE_DDR)
325 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
327 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
328 && (caslat < 2 || caslat > 5)) {
329 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
333 debug("DDR: caslat SPD bit is %d\n", caslat);
335 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
336 + (spd.clk_cycle & 0x0f));
337 max_data_rate = max_bus_clk * 2;
339 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
341 ddrc_clk = gd->mem_clk / 1000000;
342 effective_data_rate = 0;
344 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
345 if (spd.cas_lat & 0x08)
349 if (ddrc_clk <= 460 && ddrc_clk > 350)
350 effective_data_rate = 400;
351 else if (ddrc_clk <=350 && ddrc_clk > 280)
352 effective_data_rate = 333;
353 else if (ddrc_clk <= 280 && ddrc_clk > 230)
354 effective_data_rate = 266;
356 effective_data_rate = 200;
357 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
358 if (ddrc_clk <= 460 && ddrc_clk > 350) {
359 /* DDR controller clk at 350~460 */
360 effective_data_rate = 400; /* 5ns */
362 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
363 /* DDR controller clk at 280~350 */
364 effective_data_rate = 333; /* 6ns */
365 if (spd.clk_cycle2 == 0x60)
369 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
370 /* DDR controller clk at 230~280 */
371 effective_data_rate = 266; /* 7.5ns */
372 if (spd.clk_cycle3 == 0x75)
374 else if (spd.clk_cycle2 == 0x75)
378 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
379 /* DDR controller clk at 90~230 */
380 effective_data_rate = 200; /* 10ns */
381 if (spd.clk_cycle3 == 0xa0)
383 else if (spd.clk_cycle2 == 0xa0)
388 } else if (max_data_rate >= 323) { /* it is DDR 333 */
389 if (ddrc_clk <= 350 && ddrc_clk > 280) {
390 /* DDR controller clk at 280~350 */
391 effective_data_rate = 333; /* 6ns */
393 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
394 /* DDR controller clk at 230~280 */
395 effective_data_rate = 266; /* 7.5ns */
396 if (spd.clk_cycle2 == 0x75)
400 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
401 /* DDR controller clk at 90~230 */
402 effective_data_rate = 200; /* 10ns */
403 if (spd.clk_cycle3 == 0xa0)
405 else if (spd.clk_cycle2 == 0xa0)
410 } else if (max_data_rate >= 256) { /* it is DDR 266 */
411 if (ddrc_clk <= 350 && ddrc_clk > 280) {
412 /* DDR controller clk at 280~350 */
413 printf("DDR: DDR controller freq is more than "
414 "max data rate of the module\n");
416 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
417 /* DDR controller clk at 230~280 */
418 effective_data_rate = 266; /* 7.5ns */
420 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
421 /* DDR controller clk at 90~230 */
422 effective_data_rate = 200; /* 10ns */
423 if (spd.clk_cycle2 == 0xa0)
426 } else if (max_data_rate >= 190) { /* it is DDR 200 */
427 if (ddrc_clk <= 350 && ddrc_clk > 230) {
428 /* DDR controller clk at 230~350 */
429 printf("DDR: DDR controller freq is more than "
430 "max data rate of the module\n");
432 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
433 /* DDR controller clk at 90~230 */
434 effective_data_rate = 200; /* 10ns */
439 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
440 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
443 * Errata DDR6 work around: input enable 2 cycles earlier.
444 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
446 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
448 ddr->debug_reg = 0x201c0000; /* CL=2 */
449 else if (caslat == 3)
450 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
451 else if (caslat == 4)
452 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
454 __asm__ __volatile__ ("sync");
456 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
460 * Convert caslat clocks to DDR controller value.
461 * Force caslat_ctrl to be DDR Controller field-sized.
463 if (spd.mem_type == SPD_MEMTYPE_DDR) {
464 caslat_ctrl = (caslat + 1) & 0x07;
466 caslat_ctrl = (2 * caslat - 1) & 0x0f;
469 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
470 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
471 caslat, caslat_ctrl);
475 * Avoid writing for DDR I.
477 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
478 unsigned char taxpd_clk = 8; /* By the book. */
479 unsigned char tmrd_clk = 2; /* By the book. */
480 unsigned char act_pd_exit = 2; /* Empirical? */
481 unsigned char pre_pd_exit = 6; /* Empirical? */
483 ddr->timing_cfg_0 = (0
484 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
485 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
486 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
487 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
489 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
493 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
494 * use conservative value.
495 * For DDR II, they are bytes 36 and 37, in quarter nanos.
498 if (spd.mem_type == SPD_MEMTYPE_DDR) {
499 twr_clk = 3; /* Clocks */
500 twtr_clk = 1; /* Clocks */
502 twr_clk = picos_to_clk(spd.twr * 250);
503 twtr_clk = picos_to_clk(spd.twtr * 250);
509 * Calculate Trfc, in picos.
510 * DDR I: Byte 42 straight up in ns.
511 * DDR II: Byte 40 and 42 swizzled some, in ns.
513 if (spd.mem_type == SPD_MEMTYPE_DDR) {
514 trfc = spd.trfc * 1000; /* up to ps */
516 unsigned int byte40_table_ps[8] = {
527 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
528 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
530 trfc_clk = picos_to_clk(trfc);
533 * Trcd, Byte 29, from quarter nanos to ps and clocks.
535 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
538 * Convert trfc_clk to DDR controller fields. DDR I should
539 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
540 * 83xx controller has an extended REFREC field of three bits.
541 * The controller automatically adds 8 clocks to this value,
542 * so preadjust it down 8 first before splitting it up.
544 trfc_low = (trfc_clk - 8) & 0xf;
547 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
548 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
549 (trcd_clk << 20 ) | /* ACTTORW */
550 (caslat_ctrl << 16 ) | /* CASLAT */
551 (trfc_low << 12 ) | /* REFEC */
552 ((twr_clk & 0x07) << 8) | /* WRRREC */
553 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
554 ((twtr_clk & 0x07) << 0) /* WRTORD */
560 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
561 * which comes from Trcd, and also note that:
562 * add_lat + caslat must be >= 4
565 if (spd.mem_type == SPD_MEMTYPE_DDR2
566 && (odt_wr_cfg || odt_rd_cfg)
568 add_lat = 4 - caslat;
569 if ((add_lat + caslat) < 4) {
576 * Historically 0x2 == 4/8 clock delay.
577 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
580 #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
581 wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
587 * Minimum CKE Pulse Width.
588 * Four Activate Window
590 if (spd.mem_type == SPD_MEMTYPE_DDR) {
592 * This is a lie. It should really be 1, but if it is
593 * set to 1, bits overlap into the old controller's
594 * otherwise unused ACSM field. If we leave it 0, then
595 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
599 trtp_clk = 2; /* By the book. */
600 cke_min_clk = 1; /* By the book. */
601 four_act = 1; /* By the book. */
606 /* Convert SPD value from quarter nanos to picos. */
607 trtp_clk = picos_to_clk(spd.trtp * 250);
612 cke_min_clk = 3; /* By the book. */
613 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
617 * Empirically set ~MCAS-to-preamble override for DDR 2.
618 * Your milage will vary.
621 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
622 #ifdef CONFIG_SYS_DDR_CPO
623 cpo = CONFIG_SYS_DDR_CPO;
625 if (effective_data_rate == 266) {
626 cpo = 0x4; /* READ_LAT + 1/2 */
627 } else if (effective_data_rate == 333) {
628 cpo = 0x6; /* READ_LAT + 1 */
629 } else if (effective_data_rate == 400) {
630 cpo = 0x7; /* READ_LAT + 5/4 */
632 /* Automatic calibration */
638 ddr->timing_cfg_2 = (0
639 | ((add_lat & 0x7) << 28) /* ADD_LAT */
640 | ((cpo & 0x1f) << 23) /* CPO */
641 | ((wr_lat & 0x7) << 19) /* WR_LAT */
642 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
643 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
644 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
645 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
648 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
649 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
651 /* Check DIMM data bus width */
652 if (spd.dataw_lsb < 64) {
653 if (spd.mem_type == SPD_MEMTYPE_DDR)
654 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
656 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
657 debug("\n DDR DIMM: data bus width is 32 bit");
659 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
660 debug("\n DDR DIMM: data bus width is 64 bit");
663 /* Is this an ECC DDR chip? */
664 if (spd.config == 0x02)
665 debug(" with ECC\n");
667 debug(" without ECC\n");
669 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
670 Burst type is sequential
672 if (spd.mem_type == SPD_MEMTYPE_DDR) {
675 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
678 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
681 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
684 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
687 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
691 mode_odt_enable = 0x0; /* Default disabled */
692 if (odt_wr_cfg || odt_rd_cfg) {
694 * Bits 6 and 2 in Extended MRS(1)
695 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
696 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
698 mode_odt_enable = 0x40; /* 150 Ohm */
703 | (1 << (16 + 10)) /* DQS Differential disable */
704 #ifdef CONFIG_SYS_DDR_MODE_WEAK
705 | (1 << (16 + 1)) /* weak driver (~60%) */
707 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
708 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
709 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
710 | (caslat << 4) /* caslat */
711 | (burstlen << 0) /* Burst length */
714 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
717 * Clear EMRS2 and EMRS3.
719 ddr->sdram_mode2 = 0;
720 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
722 switch (spd.refresh) {
725 refresh_clk = picos_to_clk(15625000);
729 refresh_clk = picos_to_clk(3900000);
733 refresh_clk = picos_to_clk(7800000);
737 refresh_clk = picos_to_clk(31300000);
741 refresh_clk = picos_to_clk(62500000);
745 refresh_clk = picos_to_clk(125000000);
753 * Set BSTOPRE to 0x100 for page mode
754 * If auto-charge is used, set BSTOPRE = 0
756 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
757 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
763 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
764 if (odt_rd_cfg | odt_wr_cfg) {
765 odt_cfg = 0x2; /* ODT to IOs during reads */
768 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
770 | (0 << 26) /* True DQS */
771 | (odt_cfg << 21) /* ODT only read */
772 | (1 << 12) /* 1 refresh at a time */
775 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
778 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
779 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
781 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
788 * Figure out the settings for the sdram_cfg register. Build up
789 * the value in 'sdram_cfg' before writing since the write into
790 * the register will actually enable the memory controller, and all
791 * settings must be done before enabling.
793 * sdram_cfg[0] = 1 (ddr sdram logic enable)
794 * sdram_cfg[1] = 1 (self-refresh-enable)
795 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
798 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
799 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
801 if (spd.mem_type == SPD_MEMTYPE_DDR)
802 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
804 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
807 | SDRAM_CFG_MEM_EN /* DDR enable */
808 | SDRAM_CFG_SREN /* Self refresh */
809 | sdram_type /* SDRAM type */
812 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
813 if (spd.mod_attr & 0x02)
814 sdram_cfg |= SDRAM_CFG_RD_EN;
816 /* The DIMM is 32bit width */
817 if (spd.dataw_lsb < 64) {
818 if (spd.mem_type == SPD_MEMTYPE_DDR)
819 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
820 if (spd.mem_type == SPD_MEMTYPE_DDR2)
821 sdram_cfg |= SDRAM_CFG_32_BE;
826 #if defined(CONFIG_DDR_ECC)
827 /* Enable ECC with sdram_cfg[2] */
828 if (spd.config == 0x02) {
829 sdram_cfg |= 0x20000000;
831 /* disable error detection */
832 ddr->err_disable = ~ECC_ERROR_ENABLE;
833 /* set single bit error threshold to maximum value,
834 * reset counter to zero */
835 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
836 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
839 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
840 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
842 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
844 #if defined(CONFIG_DDR_2T_TIMING)
846 * Enable 2T timing by setting sdram_cfg[16].
848 sdram_cfg |= SDRAM_CFG_2T_EN;
850 /* Enable controller, and GO! */
851 ddr->sdram_cfg = sdram_cfg;
855 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
856 return memsize; /*in MBytes*/
858 #endif /* CONFIG_SPD_EEPROM */
860 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
862 * Use timebase counter, get_timer() is not availabe
863 * at this point of initialization yet.
865 static __inline__ unsigned long get_tbms (void)
868 unsigned long tbu1, tbu2;
870 unsigned long long tmp;
872 ulong tbclk = get_tbclk();
874 /* get the timebase ticks */
876 asm volatile ("mftbu %0":"=r" (tbu1):);
877 asm volatile ("mftb %0":"=r" (tbl):);
878 asm volatile ("mftbu %0":"=r" (tbu2):);
879 } while (tbu1 != tbu2);
881 /* convert ticks to ms */
882 tmp = (unsigned long long)(tbu1);
884 tmp += (unsigned long long)(tbl);
885 ms = tmp/(tbclk/1000);
891 * Initialize all of memory for ECC, then enable errors.
893 void ddr_enable_ecc(unsigned int dram_size)
895 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
896 volatile ddr83xx_t *ddr= &immap->ddr;
897 unsigned long t_start, t_end;
900 unsigned int pattern[2];
903 t_start = get_tbms();
904 pattern[0] = 0xdeadbeef;
905 pattern[1] = 0xdeadbeef;
907 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
908 dma_meminit(pattern[0], dram_size);
910 debug("ddr init: CPU FP write method\n");
912 for (p = 0; p < (u64*)(size); p++) {
913 ppcDWstore((u32*)p, pattern);
915 __asm__ __volatile__ ("sync");
921 debug("\nREADY!!\n");
922 debug("ddr init duration: %ld ms\n", t_end - t_start);
924 /* Clear All ECC Errors */
925 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
926 ddr->err_detect |= ECC_ERROR_DETECT_MME;
927 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
928 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
929 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
930 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
931 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
932 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
934 /* Disable ECC-Interrupts */
935 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
937 /* Enable errors for ECC */
938 ddr->err_disable &= ECC_ERROR_ENABLE;
940 __asm__ __volatile__ ("sync");
941 __asm__ __volatile__ ("isync");
943 #endif /* CONFIG_DDR_ECC */