2 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
8 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
36 #include <spd_sdram.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 void board_add_ram_info(int use_default)
42 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
43 volatile ddr83xx_t *ddr = &immap->ddr;
46 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
47 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
49 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
54 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
59 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
61 #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
63 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
67 #ifdef CONFIG_SPD_EEPROM
68 #ifndef CONFIG_SYS_READ_SPD
69 #define CONFIG_SYS_READ_SPD i2c_read
73 * Convert picoseconds into clock cycles (rounding up if needed).
76 picos_to_clk(int picos)
78 unsigned int mem_bus_clk;
81 mem_bus_clk = gd->mem_clk >> 1;
82 clks = picos / (1000000000 / (mem_bus_clk / 1000));
83 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
89 unsigned int banksize(unsigned char row_dens)
91 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
94 int read_spd(uint addr)
101 static void spd_debug(spd_eeprom_t *spd)
103 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
104 printf ("SPD size: %d\n", spd->info_size);
105 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
106 printf ("Memory type: %d\n", spd->mem_type);
107 printf ("Row addr: %d\n", spd->nrow_addr);
108 printf ("Column addr: %d\n", spd->ncol_addr);
109 printf ("# of rows: %d\n", spd->nrows);
110 printf ("Row density: %d\n", spd->row_dens);
111 printf ("# of banks: %d\n", spd->nbanks);
112 printf ("Data width: %d\n",
113 256 * spd->dataw_msb + spd->dataw_lsb);
114 printf ("Chip width: %d\n", spd->primw);
115 printf ("Refresh rate: %02X\n", spd->refresh);
116 printf ("CAS latencies: %02X\n", spd->cas_lat);
117 printf ("Write latencies: %02X\n", spd->write_lat);
118 printf ("tRP: %d\n", spd->trp);
119 printf ("tRCD: %d\n", spd->trcd);
122 #endif /* SPD_DEBUG */
126 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
127 volatile ddr83xx_t *ddr = &immap->ddr;
128 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
130 unsigned int n_ranks;
131 unsigned int odt_rd_cfg, odt_wr_cfg;
132 unsigned char twr_clk, twtr_clk;
133 unsigned int sdram_type;
134 unsigned int memsize;
135 unsigned int law_size;
136 unsigned char caslat, caslat_ctrl;
137 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
138 unsigned int trcd_clk, trtp_clk;
139 unsigned char cke_min_clk;
140 unsigned char add_lat, wr_lat;
141 unsigned char wr_data_delay;
142 unsigned char four_act;
144 unsigned char burstlen;
145 unsigned char odt_cfg, mode_odt_enable;
146 unsigned int max_bus_clk;
147 unsigned int max_data_rate, effective_data_rate;
148 unsigned int ddrc_clk;
149 unsigned int refresh_clk;
150 unsigned int sdram_cfg;
151 unsigned int ddrc_ecc_enable;
152 unsigned int pvr = get_pvr();
155 * First disable the memory controller (could be enabled
158 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
162 /* Read SPD parameters with I2C */
163 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
167 /* Check the memory type */
168 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
169 debug("DDR: Module mem type is %02X\n", spd.mem_type);
173 /* Check the number of physical bank */
174 if (spd.mem_type == SPD_MEMTYPE_DDR) {
177 n_ranks = (spd.nrows & 0x7) + 1;
181 printf("DDR: The number of physical bank is %02X\n", n_ranks);
185 /* Check if the number of row of the module is in the range of DDRC */
186 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
187 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
192 /* Check if the number of col of the module is in the range of DDRC */
193 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
194 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
199 #ifdef CONFIG_SYS_DDRCDR_VALUE
201 * Adjust DDR II IO voltage biasing. It just makes it work.
203 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
204 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
210 * ODT configuration recommendation from DDR Controller Chapter.
212 odt_rd_cfg = 0; /* Never assert ODT */
213 odt_wr_cfg = 0; /* Never assert ODT */
214 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
215 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
218 /* Setup DDR chip select register */
219 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
220 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
221 ddr->cs_config[0] = ( 1 << 31
224 | ((spd.nbanks == 8 ? 1 : 0) << 14)
225 | ((spd.nrow_addr - 12) << 8)
226 | (spd.ncol_addr - 8) );
228 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
229 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
232 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
233 | ((banksize(spd.row_dens) >> 23) - 1) );
234 ddr->cs_config[1] = ( 1<<31
237 | ((spd.nbanks == 8 ? 1 : 0) << 14)
238 | ((spd.nrow_addr - 12) << 8)
239 | (spd.ncol_addr - 8) );
240 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
241 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
245 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
246 ddr->cs_config[2] = ( 1 << 31
249 | ((spd.nbanks == 8 ? 1 : 0) << 14)
250 | ((spd.nrow_addr - 12) << 8)
251 | (spd.ncol_addr - 8) );
253 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
254 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
257 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
258 | ((banksize(spd.row_dens) >> 23) - 1) );
259 ddr->cs_config[3] = ( 1<<31
262 | ((spd.nbanks == 8 ? 1 : 0) << 14)
263 | ((spd.nrow_addr - 12) << 8)
264 | (spd.ncol_addr - 8) );
265 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
266 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
271 * Figure out memory size in Megabytes.
273 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
276 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
278 law_size = 19 + __ilog2(memsize);
281 * Set up LAWBAR for all of DDR.
283 ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
284 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
285 debug("DDR:bar=0x%08x\n", ecm->bar);
286 debug("DDR:ar=0x%08x\n", ecm->ar);
289 * Find the largest CAS by locating the highest 1 bit
290 * in the spd.cas_lat field. Translate it to a DDR
291 * controller field value:
293 * CAS Lat DDR I DDR II Ctrl
294 * Clocks SPD Bit SPD Bit Value
295 * ------- ------- ------- -----
306 caslat = __ilog2(spd.cas_lat);
307 if ((spd.mem_type == SPD_MEMTYPE_DDR)
309 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
311 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
312 && (caslat < 2 || caslat > 5)) {
313 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
317 debug("DDR: caslat SPD bit is %d\n", caslat);
319 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
320 + (spd.clk_cycle & 0x0f));
321 max_data_rate = max_bus_clk * 2;
323 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
325 ddrc_clk = gd->mem_clk / 1000000;
326 effective_data_rate = 0;
328 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
329 if (spd.cas_lat & 0x08)
333 if (ddrc_clk <= 460 && ddrc_clk > 350)
334 effective_data_rate = 400;
335 else if (ddrc_clk <=350 && ddrc_clk > 280)
336 effective_data_rate = 333;
337 else if (ddrc_clk <= 280 && ddrc_clk > 230)
338 effective_data_rate = 266;
340 effective_data_rate = 200;
341 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
342 if (ddrc_clk <= 460 && ddrc_clk > 350) {
343 /* DDR controller clk at 350~460 */
344 effective_data_rate = 400; /* 5ns */
346 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
347 /* DDR controller clk at 280~350 */
348 effective_data_rate = 333; /* 6ns */
349 if (spd.clk_cycle2 == 0x60)
353 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
354 /* DDR controller clk at 230~280 */
355 effective_data_rate = 266; /* 7.5ns */
356 if (spd.clk_cycle3 == 0x75)
358 else if (spd.clk_cycle2 == 0x75)
362 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
363 /* DDR controller clk at 90~230 */
364 effective_data_rate = 200; /* 10ns */
365 if (spd.clk_cycle3 == 0xa0)
367 else if (spd.clk_cycle2 == 0xa0)
372 } else if (max_data_rate >= 323) { /* it is DDR 333 */
373 if (ddrc_clk <= 350 && ddrc_clk > 280) {
374 /* DDR controller clk at 280~350 */
375 effective_data_rate = 333; /* 6ns */
377 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
378 /* DDR controller clk at 230~280 */
379 effective_data_rate = 266; /* 7.5ns */
380 if (spd.clk_cycle2 == 0x75)
384 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
385 /* DDR controller clk at 90~230 */
386 effective_data_rate = 200; /* 10ns */
387 if (spd.clk_cycle3 == 0xa0)
389 else if (spd.clk_cycle2 == 0xa0)
394 } else if (max_data_rate >= 256) { /* it is DDR 266 */
395 if (ddrc_clk <= 350 && ddrc_clk > 280) {
396 /* DDR controller clk at 280~350 */
397 printf("DDR: DDR controller freq is more than "
398 "max data rate of the module\n");
400 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
401 /* DDR controller clk at 230~280 */
402 effective_data_rate = 266; /* 7.5ns */
404 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
405 /* DDR controller clk at 90~230 */
406 effective_data_rate = 200; /* 10ns */
407 if (spd.clk_cycle2 == 0xa0)
410 } else if (max_data_rate >= 190) { /* it is DDR 200 */
411 if (ddrc_clk <= 350 && ddrc_clk > 230) {
412 /* DDR controller clk at 230~350 */
413 printf("DDR: DDR controller freq is more than "
414 "max data rate of the module\n");
416 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
417 /* DDR controller clk at 90~230 */
418 effective_data_rate = 200; /* 10ns */
423 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
424 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
427 * Errata DDR6 work around: input enable 2 cycles earlier.
428 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
430 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
432 ddr->debug_reg = 0x201c0000; /* CL=2 */
433 else if (caslat == 3)
434 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
435 else if (caslat == 4)
436 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
438 __asm__ __volatile__ ("sync");
440 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
444 * Convert caslat clocks to DDR controller value.
445 * Force caslat_ctrl to be DDR Controller field-sized.
447 if (spd.mem_type == SPD_MEMTYPE_DDR) {
448 caslat_ctrl = (caslat + 1) & 0x07;
450 caslat_ctrl = (2 * caslat - 1) & 0x0f;
453 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
454 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
455 caslat, caslat_ctrl);
459 * Avoid writing for DDR I.
461 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
462 unsigned char taxpd_clk = 8; /* By the book. */
463 unsigned char tmrd_clk = 2; /* By the book. */
464 unsigned char act_pd_exit = 2; /* Empirical? */
465 unsigned char pre_pd_exit = 6; /* Empirical? */
467 ddr->timing_cfg_0 = (0
468 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
469 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
470 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
471 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
473 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
477 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
478 * use conservative value.
479 * For DDR II, they are bytes 36 and 37, in quarter nanos.
482 if (spd.mem_type == SPD_MEMTYPE_DDR) {
483 twr_clk = 3; /* Clocks */
484 twtr_clk = 1; /* Clocks */
486 twr_clk = picos_to_clk(spd.twr * 250);
487 twtr_clk = picos_to_clk(spd.twtr * 250);
493 * Calculate Trfc, in picos.
494 * DDR I: Byte 42 straight up in ns.
495 * DDR II: Byte 40 and 42 swizzled some, in ns.
497 if (spd.mem_type == SPD_MEMTYPE_DDR) {
498 trfc = spd.trfc * 1000; /* up to ps */
500 unsigned int byte40_table_ps[8] = {
511 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
512 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
514 trfc_clk = picos_to_clk(trfc);
517 * Trcd, Byte 29, from quarter nanos to ps and clocks.
519 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
522 * Convert trfc_clk to DDR controller fields. DDR I should
523 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
524 * 83xx controller has an extended REFREC field of three bits.
525 * The controller automatically adds 8 clocks to this value,
526 * so preadjust it down 8 first before splitting it up.
528 trfc_low = (trfc_clk - 8) & 0xf;
529 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
532 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
533 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
534 (trcd_clk << 20 ) | /* ACTTORW */
535 (caslat_ctrl << 16 ) | /* CASLAT */
536 (trfc_low << 12 ) | /* REFEC */
537 ((twr_clk & 0x07) << 8) | /* WRRREC */
538 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
539 ((twtr_clk & 0x07) << 0) /* WRTORD */
545 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
546 * which comes from Trcd, and also note that:
547 * add_lat + caslat must be >= 4
550 if (spd.mem_type == SPD_MEMTYPE_DDR2
551 && (odt_wr_cfg || odt_rd_cfg)
553 add_lat = 4 - caslat;
554 if ((add_lat + caslat) < 4) {
561 * Historically 0x2 == 4/8 clock delay.
562 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
569 * Minimum CKE Pulse Width.
570 * Four Activate Window
572 if (spd.mem_type == SPD_MEMTYPE_DDR) {
574 * This is a lie. It should really be 1, but if it is
575 * set to 1, bits overlap into the old controller's
576 * otherwise unused ACSM field. If we leave it 0, then
577 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
581 trtp_clk = 2; /* By the book. */
582 cke_min_clk = 1; /* By the book. */
583 four_act = 1; /* By the book. */
588 /* Convert SPD value from quarter nanos to picos. */
589 trtp_clk = picos_to_clk(spd.trtp * 250);
594 cke_min_clk = 3; /* By the book. */
595 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
599 * Empirically set ~MCAS-to-preamble override for DDR 2.
600 * Your milage will vary.
603 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
604 if (effective_data_rate == 266) {
605 cpo = 0x4; /* READ_LAT + 1/2 */
606 } else if (effective_data_rate == 333) {
607 cpo = 0x6; /* READ_LAT + 1 */
608 } else if (effective_data_rate == 400) {
609 cpo = 0x7; /* READ_LAT + 5/4 */
611 /* Automatic calibration */
616 ddr->timing_cfg_2 = (0
617 | ((add_lat & 0x7) << 28) /* ADD_LAT */
618 | ((cpo & 0x1f) << 23) /* CPO */
619 | ((wr_lat & 0x7) << 19) /* WR_LAT */
620 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
621 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
622 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
623 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
626 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
627 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
629 /* Check DIMM data bus width */
630 if (spd.dataw_lsb < 64) {
631 if (spd.mem_type == SPD_MEMTYPE_DDR)
632 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
634 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
635 debug("\n DDR DIMM: data bus width is 32 bit");
637 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
638 debug("\n DDR DIMM: data bus width is 64 bit");
641 /* Is this an ECC DDR chip? */
642 if (spd.config == 0x02)
643 debug(" with ECC\n");
645 debug(" without ECC\n");
647 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
648 Burst type is sequential
650 if (spd.mem_type == SPD_MEMTYPE_DDR) {
653 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
656 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
659 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
662 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
665 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
669 mode_odt_enable = 0x0; /* Default disabled */
670 if (odt_wr_cfg || odt_rd_cfg) {
672 * Bits 6 and 2 in Extended MRS(1)
673 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
674 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
676 mode_odt_enable = 0x40; /* 150 Ohm */
681 | (1 << (16 + 10)) /* DQS Differential disable */
682 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
683 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
684 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
685 | (caslat << 4) /* caslat */
686 | (burstlen << 0) /* Burst length */
689 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
692 * Clear EMRS2 and EMRS3.
694 ddr->sdram_mode2 = 0;
695 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
697 switch (spd.refresh) {
700 refresh_clk = picos_to_clk(15625000);
704 refresh_clk = picos_to_clk(3900000);
708 refresh_clk = picos_to_clk(7800000);
712 refresh_clk = picos_to_clk(31300000);
716 refresh_clk = picos_to_clk(62500000);
720 refresh_clk = picos_to_clk(125000000);
728 * Set BSTOPRE to 0x100 for page mode
729 * If auto-charge is used, set BSTOPRE = 0
731 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
732 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
738 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
739 if (odt_rd_cfg | odt_wr_cfg) {
740 odt_cfg = 0x2; /* ODT to IOs during reads */
743 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
745 | (0 << 26) /* True DQS */
746 | (odt_cfg << 21) /* ODT only read */
747 | (1 << 12) /* 1 refresh at a time */
750 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
753 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
754 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
756 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
763 * Figure out the settings for the sdram_cfg register. Build up
764 * the value in 'sdram_cfg' before writing since the write into
765 * the register will actually enable the memory controller, and all
766 * settings must be done before enabling.
768 * sdram_cfg[0] = 1 (ddr sdram logic enable)
769 * sdram_cfg[1] = 1 (self-refresh-enable)
770 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
773 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
774 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
776 if (spd.mem_type == SPD_MEMTYPE_DDR)
777 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
779 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
782 | SDRAM_CFG_MEM_EN /* DDR enable */
783 | SDRAM_CFG_SREN /* Self refresh */
784 | sdram_type /* SDRAM type */
787 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
788 if (spd.mod_attr & 0x02)
789 sdram_cfg |= SDRAM_CFG_RD_EN;
791 /* The DIMM is 32bit width */
792 if (spd.dataw_lsb < 64) {
793 if (spd.mem_type == SPD_MEMTYPE_DDR)
794 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
795 if (spd.mem_type == SPD_MEMTYPE_DDR2)
796 sdram_cfg |= SDRAM_CFG_32_BE;
801 #if defined(CONFIG_DDR_ECC)
802 /* Enable ECC with sdram_cfg[2] */
803 if (spd.config == 0x02) {
804 sdram_cfg |= 0x20000000;
806 /* disable error detection */
807 ddr->err_disable = ~ECC_ERROR_ENABLE;
808 /* set single bit error threshold to maximum value,
809 * reset counter to zero */
810 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
811 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
814 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
815 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
817 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
819 #if defined(CONFIG_DDR_2T_TIMING)
821 * Enable 2T timing by setting sdram_cfg[16].
823 sdram_cfg |= SDRAM_CFG_2T_EN;
825 /* Enable controller, and GO! */
826 ddr->sdram_cfg = sdram_cfg;
830 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
831 return memsize; /*in MBytes*/
833 #endif /* CONFIG_SPD_EEPROM */
835 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
837 * Use timebase counter, get_timer() is not availabe
838 * at this point of initialization yet.
840 static __inline__ unsigned long get_tbms (void)
843 unsigned long tbu1, tbu2;
845 unsigned long long tmp;
847 ulong tbclk = get_tbclk();
849 /* get the timebase ticks */
851 asm volatile ("mftbu %0":"=r" (tbu1):);
852 asm volatile ("mftb %0":"=r" (tbl):);
853 asm volatile ("mftbu %0":"=r" (tbu2):);
854 } while (tbu1 != tbu2);
856 /* convert ticks to ms */
857 tmp = (unsigned long long)(tbu1);
859 tmp += (unsigned long long)(tbl);
860 ms = tmp/(tbclk/1000);
866 * Initialize all of memory for ECC, then enable errors.
868 void ddr_enable_ecc(unsigned int dram_size)
870 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
871 volatile ddr83xx_t *ddr= &immap->ddr;
872 unsigned long t_start, t_end;
875 unsigned int pattern[2];
878 t_start = get_tbms();
879 pattern[0] = 0xdeadbeef;
880 pattern[1] = 0xdeadbeef;
882 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
883 dma_meminit(pattern[0], dram_size);
885 debug("ddr init: CPU FP write method\n");
887 for (p = 0; p < (u64*)(size); p++) {
888 ppcDWstore((u32*)p, pattern);
890 __asm__ __volatile__ ("sync");
896 debug("\nREADY!!\n");
897 debug("ddr init duration: %ld ms\n", t_end - t_start);
899 /* Clear All ECC Errors */
900 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
901 ddr->err_detect |= ECC_ERROR_DETECT_MME;
902 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
903 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
904 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
905 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
906 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
907 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
909 /* Disable ECC-Interrupts */
910 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
912 /* Enable errors for ECC */
913 ddr->err_disable &= ECC_ERROR_ENABLE;
915 __asm__ __volatile__ ("sync");
916 __asm__ __volatile__ ("isync");
918 #endif /* CONFIG_DDR_ECC */