2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 /* ----------------------------------------------------------------- */
51 mult_t core_csb_ratio;
55 corecnf_t corecnf_tab[] = {
56 {_byp, _byp}, /* 0x00 */
57 {_byp, _byp}, /* 0x01 */
58 {_byp, _byp}, /* 0x02 */
59 {_byp, _byp}, /* 0x03 */
60 {_byp, _byp}, /* 0x04 */
61 {_byp, _byp}, /* 0x05 */
62 {_byp, _byp}, /* 0x06 */
63 {_byp, _byp}, /* 0x07 */
64 {_1x, _x2}, /* 0x08 */
65 {_1x, _x4}, /* 0x09 */
66 {_1x, _x8}, /* 0x0A */
67 {_1x, _x8}, /* 0x0B */
68 {_1_5x, _x2}, /* 0x0C */
69 {_1_5x, _x4}, /* 0x0D */
70 {_1_5x, _x8}, /* 0x0E */
71 {_1_5x, _x8}, /* 0x0F */
72 {_2x, _x2}, /* 0x10 */
73 {_2x, _x4}, /* 0x11 */
74 {_2x, _x8}, /* 0x12 */
75 {_2x, _x8}, /* 0x13 */
76 {_2_5x, _x2}, /* 0x14 */
77 {_2_5x, _x4}, /* 0x15 */
78 {_2_5x, _x8}, /* 0x16 */
79 {_2_5x, _x8}, /* 0x17 */
80 {_3x, _x2}, /* 0x18 */
81 {_3x, _x4}, /* 0x19 */
82 {_3x, _x8}, /* 0x1A */
83 {_3x, _x8}, /* 0x1B */
86 /* ----------------------------------------------------------------- */
93 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
98 u32 corecnf_tab_index;
103 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
104 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
109 #ifdef CONFIG_MPC834x
114 #if !defined(CONFIG_MPC832x)
117 #if defined(CONFIG_MPC8315)
120 #if defined(CONFIG_FSL_ESDHC)
127 #if defined(CONFIG_MPC8360)
130 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
136 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
137 defined(CONFIG_MPC837x)
141 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
145 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
148 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
150 if (im->reset.rcwh & HRCWH_PCI_HOST) {
151 #if defined(CONFIG_83XX_CLKIN)
152 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
154 pci_sync_in = 0xDEADBEEF;
157 #if defined(CONFIG_83XX_PCICLK)
158 pci_sync_in = CONFIG_83XX_PCICLK;
160 pci_sync_in = 0xDEADBEEF;
164 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
165 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
169 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
170 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
171 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
179 tsec1_clk = csb_clk / 2;
182 tsec1_clk = csb_clk / 3;
185 /* unkown SCCR_TSEC1CM value */
189 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
197 usbdr_clk = csb_clk / 2;
200 usbdr_clk = csb_clk / 3;
203 /* unkown SCCR_USBDRCM value */
208 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
209 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
210 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
218 tsec2_clk = csb_clk / 2;
221 tsec2_clk = csb_clk / 3;
224 /* unkown SCCR_TSEC2CM value */
227 #elif defined(CONFIG_MPC8313)
228 tsec2_clk = tsec1_clk;
230 if (!(sccr & SCCR_TSEC1ON))
232 if (!(sccr & SCCR_TSEC2ON))
236 #if defined(CONFIG_MPC834x)
237 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
242 usbmph_clk = csb_clk;
245 usbmph_clk = csb_clk / 2;
248 usbmph_clk = csb_clk / 3;
251 /* unkown SCCR_USBMPHCM value */
255 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
256 /* if USB MPH clock is not disabled and
257 * USB DR clock is not disabled then
258 * USB MPH & USB DR must have the same rate
263 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
271 enc_clk = csb_clk / 2;
274 enc_clk = csb_clk / 3;
277 /* unkown SCCR_ENCCM value */
281 #if defined(CONFIG_FSL_ESDHC)
282 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
290 sdhc_clk = csb_clk / 2;
293 sdhc_clk = csb_clk / 3;
296 /* unkown SCCR_SDHCCM value */
300 #if defined(CONFIG_MPC8315)
301 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
309 tdm_clk = csb_clk / 2;
312 tdm_clk = csb_clk / 3;
315 /* unkown SCCR_TDMCM value */
320 #if defined(CONFIG_MPC834x)
321 i2c1_clk = tsec2_clk;
322 #elif defined(CONFIG_MPC8360)
324 #elif defined(CONFIG_MPC832x)
326 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
328 #elif defined(CONFIG_FSL_ESDHC)
331 #if !defined(CONFIG_MPC832x)
332 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
335 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
336 defined(CONFIG_MPC837x)
337 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
342 pciexp1_clk = csb_clk;
345 pciexp1_clk = csb_clk / 2;
348 pciexp1_clk = csb_clk / 3;
351 /* unkown SCCR_PCIEXP1CM value */
355 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
360 pciexp2_clk = csb_clk;
363 pciexp2_clk = csb_clk / 2;
366 pciexp2_clk = csb_clk / 3;
369 /* unkown SCCR_PCIEXP2CM value */
374 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
375 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
383 sata_clk = csb_clk / 2;
386 sata_clk = csb_clk / 3;
389 /* unkown SCCR_SATACM value */
395 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
396 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
401 lclk_clk = lbiu_clk / lcrr;
409 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
410 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
412 #if defined(CONFIG_MPC8360)
413 mem_sec_clk = csb_clk * (1 +
414 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
417 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
418 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
419 /* corecnf_tab_index is too high, possibly worng value */
422 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
429 core_clk = (3 * csb_clk) / 2;
432 core_clk = 2 * csb_clk;
435 core_clk = (5 * csb_clk) / 2;
438 core_clk = 3 * csb_clk;
441 /* unkown core to csb ratio */
445 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
446 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
447 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
448 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
449 brg_clk = qe_clk / 2;
452 gd->csb_clk = csb_clk;
453 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
454 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
455 gd->tsec1_clk = tsec1_clk;
456 gd->tsec2_clk = tsec2_clk;
457 gd->usbdr_clk = usbdr_clk;
459 #if defined(CONFIG_MPC834x)
460 gd->usbmph_clk = usbmph_clk;
462 #if defined(CONFIG_MPC8315)
463 gd->tdm_clk = tdm_clk;
465 #if defined(CONFIG_FSL_ESDHC)
466 gd->sdhc_clk = sdhc_clk;
468 gd->core_clk = core_clk;
469 gd->i2c1_clk = i2c1_clk;
470 #if !defined(CONFIG_MPC832x)
471 gd->i2c2_clk = i2c2_clk;
473 gd->enc_clk = enc_clk;
474 gd->lbiu_clk = lbiu_clk;
475 gd->lclk_clk = lclk_clk;
476 gd->mem_clk = mem_clk;
477 #if defined(CONFIG_MPC8360)
478 gd->mem_sec_clk = mem_sec_clk;
480 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
482 gd->brg_clk = brg_clk;
484 #if defined(CONFIG_MPC837x)
485 gd->pciexp1_clk = pciexp1_clk;
486 gd->pciexp2_clk = pciexp2_clk;
488 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
489 gd->sata_clk = sata_clk;
491 gd->pci_clk = pci_sync_in;
492 gd->cpu_clk = gd->core_clk;
493 gd->bus_clk = gd->csb_clk;
498 /********************************************
500 * return system bus freq in Hz
501 *********************************************/
502 ulong get_bus_freq(ulong dummy)
507 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
511 printf("Clock configuration:\n");
512 printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
513 printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
514 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
515 printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
516 printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
518 printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
519 printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));
520 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
521 #if defined(CONFIG_MPC8360)
522 printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
524 printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
525 printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
526 #if !defined(CONFIG_MPC832x)
527 printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
529 #if defined(CONFIG_MPC8315)
530 printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
532 #if defined(CONFIG_FSL_ESDHC)
533 printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
535 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
536 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
537 printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
538 printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
539 printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
541 #if defined(CONFIG_MPC834x)
542 printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
544 #if defined(CONFIG_MPC837x)
545 printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
546 printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
548 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
549 printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk));
554 U_BOOT_CMD(clocks, 1, 0, do_clocks,
555 "print clock configuration",