git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc83xx/speed.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2000-2002
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   7  */
   8
   9 #include <common.h>
  10 #include <mpc83xx.h>
  11 #include <command.h>
  12 #include <asm/processor.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 /* ----------------------------------------------------------------- */
  17
  18 typedef enum {
  19         _unk,
  20         _off,
  21         _byp,
  22         _x8,
  23         _x4,
  24         _x2,
  25         _x1,
  26         _1x,
  27         _1_5x,
  28         _2x,
  29         _2_5x,
  30         _3x
  31 } mult_t;
  32
  33 typedef struct {
  34         mult_t core_csb_ratio;
  35         mult_t vco_divider;
  36 } corecnf_t;
  37
  38 static corecnf_t corecnf_tab[] = {
  39         {_byp, _byp},           /* 0x00 */
  40         {_byp, _byp},           /* 0x01 */
  41         {_byp, _byp},           /* 0x02 */
  42         {_byp, _byp},           /* 0x03 */
  43         {_byp, _byp},           /* 0x04 */
  44         {_byp, _byp},           /* 0x05 */
  45         {_byp, _byp},           /* 0x06 */
  46         {_byp, _byp},           /* 0x07 */
  47         {_1x, _x2},             /* 0x08 */
  48         {_1x, _x4},             /* 0x09 */
  49         {_1x, _x8},             /* 0x0A */
  50         {_1x, _x8},             /* 0x0B */
  51         {_1_5x, _x2},           /* 0x0C */
  52         {_1_5x, _x4},           /* 0x0D */
  53         {_1_5x, _x8},           /* 0x0E */
  54         {_1_5x, _x8},           /* 0x0F */
  55         {_2x, _x2},             /* 0x10 */
  56         {_2x, _x4},             /* 0x11 */
  57         {_2x, _x8},             /* 0x12 */
  58         {_2x, _x8},             /* 0x13 */
  59         {_2_5x, _x2},           /* 0x14 */
  60         {_2_5x, _x4},           /* 0x15 */
  61         {_2_5x, _x8},           /* 0x16 */
  62         {_2_5x, _x8},           /* 0x17 */
  63         {_3x, _x2},             /* 0x18 */
  64         {_3x, _x4},             /* 0x19 */
  65         {_3x, _x8},             /* 0x1A */
  66         {_3x, _x8},             /* 0x1B */
  67 };
  68
  69 /* ----------------------------------------------------------------- */
  70
  71 /*
  72  *
  73  */
  74 int get_clocks(void)
  75 {
  76         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  77         u32 pci_sync_in;
  78         u8 spmf;
  79         u8 clkin_div;
  80         u32 sccr;
  81         u32 corecnf_tab_index;
  82         u8 corepll;
  83         u32 lcrr;
  84
  85         u32 csb_clk;
  86 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
  87         defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
  88         u32 tsec1_clk;
  89         u32 tsec2_clk;
  90         u32 usbdr_clk;
  91 #elif defined(CONFIG_MPC8309)
  92         u32 usbdr_clk;
  93 #endif
  94 #ifdef CONFIG_MPC834x
  95         u32 usbmph_clk;
  96 #endif
  97         u32 core_clk;
  98         u32 i2c1_clk;
  99 #if !defined(CONFIG_MPC832x)
 100         u32 i2c2_clk;
 101 #endif
 102 #if defined(CONFIG_MPC8315)
 103         u32 tdm_clk;
 104 #endif
 105 #if defined(CONFIG_FSL_ESDHC)
 106         u32 sdhc_clk;
 107 #endif
 108 #if !defined(CONFIG_MPC8309)
 109         u32 enc_clk;
 110 #endif
 111         u32 lbiu_clk;
 112         u32 lclk_clk;
 113         u32 mem_clk;
 114 #if defined(CONFIG_MPC8360)
 115         u32 mem_sec_clk;
 116 #endif
 117 #if defined(CONFIG_QE)
 118         u32 qepmf;
 119         u32 qepdf;
 120         u32 qe_clk;
 121         u32 brg_clk;
 122 #endif
 123 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 124         defined(CONFIG_MPC837x)
 125         u32 pciexp1_clk;
 126         u32 pciexp2_clk;
 127 #endif
 128 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 129         u32 sata_clk;
 130 #endif
 131
 132         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 133                 return -1;
 134
 135         clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 136
 137         if (im->reset.rcwh & HRCWH_PCI_HOST) {
 138 #if defined(CONFIG_83XX_CLKIN)
 139                 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
 140 #else
 141                 pci_sync_in = 0xDEADBEEF;
 142 #endif
 143         } else {
 144 #if defined(CONFIG_83XX_PCICLK)
 145                 pci_sync_in = CONFIG_83XX_PCICLK;
 146 #else
 147                 pci_sync_in = 0xDEADBEEF;
 148 #endif
 149         }
 150
 151         spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 152         csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 153
 154         sccr = im->clk.sccr;
 155
 156 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 157         defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 158         switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 159         case 0:
 160                 tsec1_clk = 0;
 161                 break;
 162         case 1:
 163                 tsec1_clk = csb_clk;
 164                 break;
 165         case 2:
 166                 tsec1_clk = csb_clk / 2;
 167                 break;
 168         case 3:
 169                 tsec1_clk = csb_clk / 3;
 170                 break;
 171         default:
 172                 /* unknown SCCR_TSEC1CM value */
 173                 return -2;
 174         }
 175 #endif
 176
 177 #if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
 178         defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 179         switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
 180         case 0:
 181                 usbdr_clk = 0;
 182                 break;
 183         case 1:
 184                 usbdr_clk = csb_clk;
 185                 break;
 186         case 2:
 187                 usbdr_clk = csb_clk / 2;
 188                 break;
 189         case 3:
 190                 usbdr_clk = csb_clk / 3;
 191                 break;
 192         default:
 193                 /* unknown SCCR_USBDRCM value */
 194                 return -3;
 195         }
 196 #endif
 197
 198 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
 199         defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 200         switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 201         case 0:
 202                 tsec2_clk = 0;
 203                 break;
 204         case 1:
 205                 tsec2_clk = csb_clk;
 206                 break;
 207         case 2:
 208                 tsec2_clk = csb_clk / 2;
 209                 break;
 210         case 3:
 211                 tsec2_clk = csb_clk / 3;
 212                 break;
 213         default:
 214                 /* unknown SCCR_TSEC2CM value */
 215                 return -4;
 216         }
 217 #elif defined(CONFIG_MPC8313)
 218         tsec2_clk = tsec1_clk;
 219
 220         if (!(sccr & SCCR_TSEC1ON))
 221                 tsec1_clk = 0;
 222         if (!(sccr & SCCR_TSEC2ON))
 223                 tsec2_clk = 0;
 224 #endif
 225
 226 #if defined(CONFIG_MPC834x)
 227         switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 228         case 0:
 229                 usbmph_clk = 0;
 230                 break;
 231         case 1:
 232                 usbmph_clk = csb_clk;
 233                 break;
 234         case 2:
 235                 usbmph_clk = csb_clk / 2;
 236                 break;
 237         case 3:
 238                 usbmph_clk = csb_clk / 3;
 239                 break;
 240         default:
 241                 /* unknown SCCR_USBMPHCM value */
 242                 return -5;
 243         }
 244
 245         if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
 246                 /* if USB MPH clock is not disabled and
 247                  * USB DR clock is not disabled then
 248                  * USB MPH & USB DR must have the same rate
 249                  */
 250                 return -6;
 251         }
 252 #endif
 253 #if !defined(CONFIG_MPC8309)
 254         switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 255         case 0:
 256                 enc_clk = 0;
 257                 break;
 258         case 1:
 259                 enc_clk = csb_clk;
 260                 break;
 261         case 2:
 262                 enc_clk = csb_clk / 2;
 263                 break;
 264         case 3:
 265                 enc_clk = csb_clk / 3;
 266                 break;
 267         default:
 268                 /* unknown SCCR_ENCCM value */
 269                 return -7;
 270         }
 271 #endif
 272
 273 #if defined(CONFIG_FSL_ESDHC)
 274         switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
 275         case 0:
 276                 sdhc_clk = 0;
 277                 break;
 278         case 1:
 279                 sdhc_clk = csb_clk;
 280                 break;
 281         case 2:
 282                 sdhc_clk = csb_clk / 2;
 283                 break;
 284         case 3:
 285                 sdhc_clk = csb_clk / 3;
 286                 break;
 287         default:
 288                 /* unknown SCCR_SDHCCM value */
 289                 return -8;
 290         }
 291 #endif
 292 #if defined(CONFIG_MPC8315)
 293         switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
 294         case 0:
 295                 tdm_clk = 0;
 296                 break;
 297         case 1:
 298                 tdm_clk = csb_clk;
 299                 break;
 300         case 2:
 301                 tdm_clk = csb_clk / 2;
 302                 break;
 303         case 3:
 304                 tdm_clk = csb_clk / 3;
 305                 break;
 306         default:
 307                 /* unknown SCCR_TDMCM value */
 308                 return -8;
 309         }
 310 #endif
 311
 312 #if defined(CONFIG_MPC834x)
 313         i2c1_clk = tsec2_clk;
 314 #elif defined(CONFIG_MPC8360)
 315         i2c1_clk = csb_clk;
 316 #elif defined(CONFIG_MPC832x)
 317         i2c1_clk = enc_clk;
 318 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
 319         i2c1_clk = enc_clk;
 320 #elif defined(CONFIG_FSL_ESDHC)
 321         i2c1_clk = sdhc_clk;
 322 #elif defined(CONFIG_MPC837x)
 323         i2c1_clk = enc_clk;
 324 #elif defined(CONFIG_MPC8309)
 325         i2c1_clk = csb_clk;
 326 #endif
 327 #if !defined(CONFIG_MPC832x)
 328         i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
 329 #endif
 330
 331 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 332         defined(CONFIG_MPC837x)
 333         switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
 334         case 0:
 335                 pciexp1_clk = 0;
 336                 break;
 337         case 1:
 338                 pciexp1_clk = csb_clk;
 339                 break;
 340         case 2:
 341                 pciexp1_clk = csb_clk / 2;
 342                 break;
 343         case 3:
 344                 pciexp1_clk = csb_clk / 3;
 345                 break;
 346         default:
 347                 /* unknown SCCR_PCIEXP1CM value */
 348                 return -9;
 349         }
 350
 351         switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
 352         case 0:
 353                 pciexp2_clk = 0;
 354                 break;
 355         case 1:
 356                 pciexp2_clk = csb_clk;
 357                 break;
 358         case 2:
 359                 pciexp2_clk = csb_clk / 2;
 360                 break;
 361         case 3:
 362                 pciexp2_clk = csb_clk / 3;
 363                 break;
 364         default:
 365                 /* unknown SCCR_PCIEXP2CM value */
 366                 return -10;
 367         }
 368 #endif
 369
 370 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 371         switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
 372         case 0:
 373                 sata_clk = 0;
 374                 break;
 375         case 1:
 376                 sata_clk = csb_clk;
 377                 break;
 378         case 2:
 379                 sata_clk = csb_clk / 2;
 380                 break;
 381         case 3:
 382                 sata_clk = csb_clk / 3;
 383                 break;
 384         default:
 385                 /* unknown SCCR_SATA1CM value */
 386                 return -11;
 387         }
 388 #endif
 389
 390         lbiu_clk = csb_clk *
 391                    (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
 392         lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 393         switch (lcrr) {
 394         case 2:
 395         case 4:
 396         case 8:
 397                 lclk_clk = lbiu_clk / lcrr;
 398                 break;
 399         default:
 400                 /* unknown lcrr */
 401                 return -12;
 402         }
 403
 404         mem_clk = csb_clk *
 405                   (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
 406         corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
 407
 408 #if defined(CONFIG_MPC8360)
 409         mem_sec_clk = csb_clk * (1 +
 410                        ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
 411 #endif
 412
 413         corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
 414         if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
 415                 /* corecnf_tab_index is too high, possibly wrong value */
 416                 return -11;
 417         }
 418         switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
 419         case _byp:
 420         case _x1:
 421         case _1x:
 422                 core_clk = csb_clk;
 423                 break;
 424         case _1_5x:
 425                 core_clk = (3 * csb_clk) / 2;
 426                 break;
 427         case _2x:
 428                 core_clk = 2 * csb_clk;
 429                 break;
 430         case _2_5x:
 431                 core_clk = (5 * csb_clk) / 2;
 432                 break;
 433         case _3x:
 434                 core_clk = 3 * csb_clk;
 435                 break;
 436         default:
 437                 /* unknown core to csb ratio */
 438                 return -13;
 439         }
 440
 441 #if defined(CONFIG_QE)
 442         qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
 443         qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
 444         qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
 445         brg_clk = qe_clk / 2;
 446 #endif
 447
 448         gd->arch.csb_clk = csb_clk;
 449 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 450         defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 451         gd->arch.tsec1_clk = tsec1_clk;
 452         gd->arch.tsec2_clk = tsec2_clk;
 453         gd->arch.usbdr_clk = usbdr_clk;
 454 #elif defined(CONFIG_MPC8309)
 455         gd->arch.usbdr_clk = usbdr_clk;
 456 #endif
 457 #if defined(CONFIG_MPC834x)
 458         gd->arch.usbmph_clk = usbmph_clk;
 459 #endif
 460 #if defined(CONFIG_MPC8315)
 461         gd->arch.tdm_clk = tdm_clk;
 462 #endif
 463 #if defined(CONFIG_FSL_ESDHC)
 464         gd->arch.sdhc_clk = sdhc_clk;
 465 #endif
 466         gd->arch.core_clk = core_clk;
 467         gd->arch.i2c1_clk = i2c1_clk;
 468 #if !defined(CONFIG_MPC832x)
 469         gd->arch.i2c2_clk = i2c2_clk;
 470 #endif
 471 #if !defined(CONFIG_MPC8309)
 472         gd->arch.enc_clk = enc_clk;
 473 #endif
 474         gd->arch.lbiu_clk = lbiu_clk;
 475         gd->arch.lclk_clk = lclk_clk;
 476         gd->mem_clk = mem_clk;
 477 #if defined(CONFIG_MPC8360)
 478         gd->arch.mem_sec_clk = mem_sec_clk;
 479 #endif
 480 #if defined(CONFIG_QE)
 481         gd->arch.qe_clk = qe_clk;
 482         gd->arch.brg_clk = brg_clk;
 483 #endif
 484 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 485         defined(CONFIG_MPC837x)
 486         gd->arch.pciexp1_clk = pciexp1_clk;
 487         gd->arch.pciexp2_clk = pciexp2_clk;
 488 #endif
 489 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 490         gd->arch.sata_clk = sata_clk;
 491 #endif
 492         gd->pci_clk = pci_sync_in;
 493         gd->cpu_clk = gd->arch.core_clk;
 494         gd->bus_clk = gd->arch.csb_clk;
 495         return 0;
 496
 497 }
 498
 499 /********************************************
 500  * get_bus_freq
 501  * return system bus freq in Hz
 502  *********************************************/
 503 ulong get_bus_freq(ulong dummy)
 504 {
 505         return gd->arch.csb_clk;
 506 }
 507
 508 /********************************************
 509  * get_ddr_freq
 510  * return ddr bus freq in Hz
 511  *********************************************/
 512 ulong get_ddr_freq(ulong dummy)
 513 {
 514         return gd->mem_clk;
 515 }
 516
 517 static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 518 {
 519         char buf[32];
 520
 521         printf("Clock configuration:\n");
 522         printf("  Core:                %-4s MHz\n",
 523                strmhz(buf, gd->arch.core_clk));
 524         printf("  Coherent System Bus: %-4s MHz\n",
 525                strmhz(buf, gd->arch.csb_clk));
 526 #if defined(CONFIG_QE)
 527         printf("  QE:                  %-4s MHz\n",
 528                strmhz(buf, gd->arch.qe_clk));
 529         printf("  BRG:                 %-4s MHz\n",
 530                strmhz(buf, gd->arch.brg_clk));
 531 #endif
 532         printf("  Local Bus Controller:%-4s MHz\n",
 533                strmhz(buf, gd->arch.lbiu_clk));
 534         printf("  Local Bus:           %-4s MHz\n",
 535                strmhz(buf, gd->arch.lclk_clk));
 536         printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
 537 #if defined(CONFIG_MPC8360)
 538         printf("  DDR Secondary:       %-4s MHz\n",
 539                strmhz(buf, gd->arch.mem_sec_clk));
 540 #endif
 541 #if !defined(CONFIG_MPC8309)
 542         printf("  SEC:                 %-4s MHz\n",
 543                strmhz(buf, gd->arch.enc_clk));
 544 #endif
 545         printf("  I2C1:                %-4s MHz\n",
 546                strmhz(buf, gd->arch.i2c1_clk));
 547 #if !defined(CONFIG_MPC832x)
 548         printf("  I2C2:                %-4s MHz\n",
 549                strmhz(buf, gd->arch.i2c2_clk));
 550 #endif
 551 #if defined(CONFIG_MPC8315)
 552         printf("  TDM:                 %-4s MHz\n",
 553                strmhz(buf, gd->arch.tdm_clk));
 554 #endif
 555 #if defined(CONFIG_FSL_ESDHC)
 556         printf("  SDHC:                %-4s MHz\n",
 557                strmhz(buf, gd->arch.sdhc_clk));
 558 #endif
 559 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 560         defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 561         printf("  TSEC1:               %-4s MHz\n",
 562                strmhz(buf, gd->arch.tsec1_clk));
 563         printf("  TSEC2:               %-4s MHz\n",
 564                strmhz(buf, gd->arch.tsec2_clk));
 565         printf("  USB DR:              %-4s MHz\n",
 566                strmhz(buf, gd->arch.usbdr_clk));
 567 #elif defined(CONFIG_MPC8309)
 568         printf("  USB DR:              %-4s MHz\n",
 569                strmhz(buf, gd->arch.usbdr_clk));
 570 #endif
 571 #if defined(CONFIG_MPC834x)
 572         printf("  USB MPH:             %-4s MHz\n",
 573                strmhz(buf, gd->arch.usbmph_clk));
 574 #endif
 575 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 576         defined(CONFIG_MPC837x)
 577         printf("  PCIEXP1:             %-4s MHz\n",
 578                strmhz(buf, gd->arch.pciexp1_clk));
 579         printf("  PCIEXP2:             %-4s MHz\n",
 580                strmhz(buf, gd->arch.pciexp2_clk));
 581 #endif
 582 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 583         printf("  SATA:                %-4s MHz\n",
 584                strmhz(buf, gd->arch.sata_clk));
 585 #endif
 586         return 0;
 587 }
 588
 589 U_BOOT_CMD(clocks, 1, 0, do_clocks,
 590         "print clock configuration",
 591         "    clocks"
 592 );