1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
12 #include <asm/processor.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 /* ----------------------------------------------------------------- */
34 mult_t core_csb_ratio;
38 static corecnf_t corecnf_tab[] = {
39 {_byp, _byp}, /* 0x00 */
40 {_byp, _byp}, /* 0x01 */
41 {_byp, _byp}, /* 0x02 */
42 {_byp, _byp}, /* 0x03 */
43 {_byp, _byp}, /* 0x04 */
44 {_byp, _byp}, /* 0x05 */
45 {_byp, _byp}, /* 0x06 */
46 {_byp, _byp}, /* 0x07 */
47 {_1x, _x2}, /* 0x08 */
48 {_1x, _x4}, /* 0x09 */
49 {_1x, _x8}, /* 0x0A */
50 {_1x, _x8}, /* 0x0B */
51 {_1_5x, _x2}, /* 0x0C */
52 {_1_5x, _x4}, /* 0x0D */
53 {_1_5x, _x8}, /* 0x0E */
54 {_1_5x, _x8}, /* 0x0F */
55 {_2x, _x2}, /* 0x10 */
56 {_2x, _x4}, /* 0x11 */
57 {_2x, _x8}, /* 0x12 */
58 {_2x, _x8}, /* 0x13 */
59 {_2_5x, _x2}, /* 0x14 */
60 {_2_5x, _x4}, /* 0x15 */
61 {_2_5x, _x8}, /* 0x16 */
62 {_2_5x, _x8}, /* 0x17 */
63 {_3x, _x2}, /* 0x18 */
64 {_3x, _x4}, /* 0x19 */
65 {_3x, _x8}, /* 0x1A */
66 {_3x, _x8}, /* 0x1B */
69 /* ----------------------------------------------------------------- */
76 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
81 u32 corecnf_tab_index;
86 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
87 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
91 #elif defined(CONFIG_MPC8309)
99 #if !defined(CONFIG_MPC832x)
102 #if defined(CONFIG_MPC8315)
105 #if defined(CONFIG_FSL_ESDHC)
108 #if !defined(CONFIG_MPC8309)
114 #if defined(CONFIG_MPC8360)
117 #if defined(CONFIG_QE)
123 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
124 defined(CONFIG_MPC837x)
128 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
132 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
135 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
137 if (im->reset.rcwh & HRCWH_PCI_HOST) {
138 #if defined(CONFIG_83XX_CLKIN)
139 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
141 pci_sync_in = 0xDEADBEEF;
144 #if defined(CONFIG_83XX_PCICLK)
145 pci_sync_in = CONFIG_83XX_PCICLK;
147 pci_sync_in = 0xDEADBEEF;
151 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
152 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
156 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
157 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
158 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
166 tsec1_clk = csb_clk / 2;
169 tsec1_clk = csb_clk / 3;
172 /* unknown SCCR_TSEC1CM value */
177 #if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
178 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
179 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
187 usbdr_clk = csb_clk / 2;
190 usbdr_clk = csb_clk / 3;
193 /* unknown SCCR_USBDRCM value */
198 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
199 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
200 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
208 tsec2_clk = csb_clk / 2;
211 tsec2_clk = csb_clk / 3;
214 /* unknown SCCR_TSEC2CM value */
217 #elif defined(CONFIG_MPC8313)
218 tsec2_clk = tsec1_clk;
220 if (!(sccr & SCCR_TSEC1ON))
222 if (!(sccr & SCCR_TSEC2ON))
226 #if defined(CONFIG_MPC834x)
227 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
232 usbmph_clk = csb_clk;
235 usbmph_clk = csb_clk / 2;
238 usbmph_clk = csb_clk / 3;
241 /* unknown SCCR_USBMPHCM value */
245 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
246 /* if USB MPH clock is not disabled and
247 * USB DR clock is not disabled then
248 * USB MPH & USB DR must have the same rate
253 #if !defined(CONFIG_MPC8309)
254 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
262 enc_clk = csb_clk / 2;
265 enc_clk = csb_clk / 3;
268 /* unknown SCCR_ENCCM value */
273 #if defined(CONFIG_FSL_ESDHC)
274 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
282 sdhc_clk = csb_clk / 2;
285 sdhc_clk = csb_clk / 3;
288 /* unknown SCCR_SDHCCM value */
292 #if defined(CONFIG_MPC8315)
293 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
301 tdm_clk = csb_clk / 2;
304 tdm_clk = csb_clk / 3;
307 /* unknown SCCR_TDMCM value */
312 #if defined(CONFIG_MPC834x)
313 i2c1_clk = tsec2_clk;
314 #elif defined(CONFIG_MPC8360)
316 #elif defined(CONFIG_MPC832x)
318 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
320 #elif defined(CONFIG_FSL_ESDHC)
322 #elif defined(CONFIG_MPC837x)
324 #elif defined(CONFIG_MPC8309)
327 #if !defined(CONFIG_MPC832x)
328 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
331 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
332 defined(CONFIG_MPC837x)
333 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
338 pciexp1_clk = csb_clk;
341 pciexp1_clk = csb_clk / 2;
344 pciexp1_clk = csb_clk / 3;
347 /* unknown SCCR_PCIEXP1CM value */
351 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
356 pciexp2_clk = csb_clk;
359 pciexp2_clk = csb_clk / 2;
362 pciexp2_clk = csb_clk / 3;
365 /* unknown SCCR_PCIEXP2CM value */
370 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
371 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
379 sata_clk = csb_clk / 2;
382 sata_clk = csb_clk / 3;
385 /* unknown SCCR_SATA1CM value */
391 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
392 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
397 lclk_clk = lbiu_clk / lcrr;
405 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
406 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
408 #if defined(CONFIG_MPC8360)
409 mem_sec_clk = csb_clk * (1 +
410 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
413 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
414 if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
415 /* corecnf_tab_index is too high, possibly wrong value */
418 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
425 core_clk = (3 * csb_clk) / 2;
428 core_clk = 2 * csb_clk;
431 core_clk = (5 * csb_clk) / 2;
434 core_clk = 3 * csb_clk;
437 /* unknown core to csb ratio */
441 #if defined(CONFIG_QE)
442 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
443 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
444 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
445 brg_clk = qe_clk / 2;
448 gd->arch.csb_clk = csb_clk;
449 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
450 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
451 gd->arch.tsec1_clk = tsec1_clk;
452 gd->arch.tsec2_clk = tsec2_clk;
453 gd->arch.usbdr_clk = usbdr_clk;
454 #elif defined(CONFIG_MPC8309)
455 gd->arch.usbdr_clk = usbdr_clk;
457 #if defined(CONFIG_MPC834x)
458 gd->arch.usbmph_clk = usbmph_clk;
460 #if defined(CONFIG_MPC8315)
461 gd->arch.tdm_clk = tdm_clk;
463 #if defined(CONFIG_FSL_ESDHC)
464 gd->arch.sdhc_clk = sdhc_clk;
466 gd->arch.core_clk = core_clk;
467 gd->arch.i2c1_clk = i2c1_clk;
468 #if !defined(CONFIG_MPC832x)
469 gd->arch.i2c2_clk = i2c2_clk;
471 #if !defined(CONFIG_MPC8309)
472 gd->arch.enc_clk = enc_clk;
474 gd->arch.lbiu_clk = lbiu_clk;
475 gd->arch.lclk_clk = lclk_clk;
476 gd->mem_clk = mem_clk;
477 #if defined(CONFIG_MPC8360)
478 gd->arch.mem_sec_clk = mem_sec_clk;
480 #if defined(CONFIG_QE)
481 gd->arch.qe_clk = qe_clk;
482 gd->arch.brg_clk = brg_clk;
484 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
485 defined(CONFIG_MPC837x)
486 gd->arch.pciexp1_clk = pciexp1_clk;
487 gd->arch.pciexp2_clk = pciexp2_clk;
489 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
490 gd->arch.sata_clk = sata_clk;
492 gd->pci_clk = pci_sync_in;
493 gd->cpu_clk = gd->arch.core_clk;
494 gd->bus_clk = gd->arch.csb_clk;
499 /********************************************
501 * return system bus freq in Hz
502 *********************************************/
503 ulong get_bus_freq(ulong dummy)
505 return gd->arch.csb_clk;
508 /********************************************
510 * return ddr bus freq in Hz
511 *********************************************/
512 ulong get_ddr_freq(ulong dummy)
517 static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
521 printf("Clock configuration:\n");
522 printf(" Core: %-4s MHz\n",
523 strmhz(buf, gd->arch.core_clk));
524 printf(" Coherent System Bus: %-4s MHz\n",
525 strmhz(buf, gd->arch.csb_clk));
526 #if defined(CONFIG_QE)
527 printf(" QE: %-4s MHz\n",
528 strmhz(buf, gd->arch.qe_clk));
529 printf(" BRG: %-4s MHz\n",
530 strmhz(buf, gd->arch.brg_clk));
532 printf(" Local Bus Controller:%-4s MHz\n",
533 strmhz(buf, gd->arch.lbiu_clk));
534 printf(" Local Bus: %-4s MHz\n",
535 strmhz(buf, gd->arch.lclk_clk));
536 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
537 #if defined(CONFIG_MPC8360)
538 printf(" DDR Secondary: %-4s MHz\n",
539 strmhz(buf, gd->arch.mem_sec_clk));
541 #if !defined(CONFIG_MPC8309)
542 printf(" SEC: %-4s MHz\n",
543 strmhz(buf, gd->arch.enc_clk));
545 printf(" I2C1: %-4s MHz\n",
546 strmhz(buf, gd->arch.i2c1_clk));
547 #if !defined(CONFIG_MPC832x)
548 printf(" I2C2: %-4s MHz\n",
549 strmhz(buf, gd->arch.i2c2_clk));
551 #if defined(CONFIG_MPC8315)
552 printf(" TDM: %-4s MHz\n",
553 strmhz(buf, gd->arch.tdm_clk));
555 #if defined(CONFIG_FSL_ESDHC)
556 printf(" SDHC: %-4s MHz\n",
557 strmhz(buf, gd->arch.sdhc_clk));
559 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
560 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
561 printf(" TSEC1: %-4s MHz\n",
562 strmhz(buf, gd->arch.tsec1_clk));
563 printf(" TSEC2: %-4s MHz\n",
564 strmhz(buf, gd->arch.tsec2_clk));
565 printf(" USB DR: %-4s MHz\n",
566 strmhz(buf, gd->arch.usbdr_clk));
567 #elif defined(CONFIG_MPC8309)
568 printf(" USB DR: %-4s MHz\n",
569 strmhz(buf, gd->arch.usbdr_clk));
571 #if defined(CONFIG_MPC834x)
572 printf(" USB MPH: %-4s MHz\n",
573 strmhz(buf, gd->arch.usbmph_clk));
575 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
576 defined(CONFIG_MPC837x)
577 printf(" PCIEXP1: %-4s MHz\n",
578 strmhz(buf, gd->arch.pciexp1_clk));
579 printf(" PCIEXP2: %-4s MHz\n",
580 strmhz(buf, gd->arch.pciexp2_clk));
582 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
583 printf(" SATA: %-4s MHz\n",
584 strmhz(buf, gd->arch.sata_clk));
589 U_BOOT_CMD(clocks, 1, 0, do_clocks,
590 "print clock configuration",