2 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 DECLARE_GLOBAL_DATA_PTR;
13 * Breathe some life into the CPU...
15 * Set up the memory map,
16 * initialize a bunch of registers,
17 * initialize the UPM's
19 void cpu_init_f (volatile immap_t * im)
21 /* Pointer is writable since we allocated a register for it */
22 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
24 /* global data region was cleared in start.S */
26 /* system performance tweaking */
28 #ifdef CONFIG_SYS_ACR_PIPE_DEP
29 /* Arbiter pipeline depth */
30 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
31 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
34 #ifdef CONFIG_SYS_ACR_RPTCNT
35 /* Arbiter repeat count */
36 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
37 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
40 #ifdef CONFIG_SYS_SPCR_OPT
41 /* Optimize transactions between CSB and other devices */
42 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
43 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
46 /* Enable Time Base & Decrementer (so we will have udelay()) */
47 im->sysconf.spcr |= SPCR_TBEN;
49 /* DDR control driver register */
50 #ifdef CONFIG_SYS_DDRCDR
51 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
53 /* Output buffer impedance register */
54 #ifdef CONFIG_SYS_OBIR
55 im->sysconf.obir = CONFIG_SYS_OBIR;
62 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
63 * addresses - these have to be modified later when FLASH size
67 #if defined(CONFIG_SYS_NAND_BR_PRELIM) \
68 && defined(CONFIG_SYS_NAND_OR_PRELIM) \
69 && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
70 && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
71 set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
72 set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
73 im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
74 im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
76 #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
81 * Get timebase clock frequency (like cpu_clk in Hz)
83 unsigned long get_tbclk(void)
85 return (gd->bus_clk + 3L) / 4L;
88 void puts(const char *str)