2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
30 #include <asm-offsets.h>
33 #ifndef CONFIG_IDENT_STRING
34 #define CONFIG_IDENT_STRING "MPC83XX"
38 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
39 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
41 #include <ppc_asm.tmpl>
44 #include <asm/cache.h>
46 #include <asm/u-boot.h>
48 /* We don't want the MMU yet.
53 * Floating Point enable, Machine Check and Recoverable Interr.
56 #define MSR_KERNEL (MSR_FP|MSR_RI)
58 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
61 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
62 #define CONFIG_SYS_FLASHBOOT
66 * Set up GOT: Global Offset Table
68 * Use r12 to access the GOT
71 GOT_ENTRY(_GOT2_TABLE_)
72 GOT_ENTRY(__bss_start)
73 GOT_ENTRY(__bss_end__)
75 #ifndef CONFIG_NAND_SPL
76 GOT_ENTRY(_FIXUP_TABLE_)
78 GOT_ENTRY(_start_of_vectors)
79 GOT_ENTRY(_end_of_vectors)
80 GOT_ENTRY(transfer_to_handler)
85 * The Hard Reset Configuration Word (HRCW) table is in the first 64
86 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
87 * times so the processor can fetch it out of flash whether the flash
88 * is 8, 16, 32, or 64 bits wide (hardware trickery).
91 #define _HRCW_TABLE_ENTRY(w) \
92 .fill 8,1,(((w)>>24)&0xff); \
93 .fill 8,1,(((w)>>16)&0xff); \
94 .fill 8,1,(((w)>> 8)&0xff); \
95 .fill 8,1,(((w) )&0xff)
97 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
98 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
101 * Magic number and version string - put it after the HRCW since it
102 * cannot be first in flash like it is in many other processors.
104 .long 0x27051956 /* U-Boot Magic Number */
106 .globl version_string
108 .ascii U_BOOT_VERSION_STRING, "\0"
112 .globl enable_addr_trans
114 /* enable address translation */
116 ori r5, r5, (MSR_IR | MSR_DR)
121 .globl disable_addr_trans
123 /* disable address translation */
126 andi. r0, r3, (MSR_IR | MSR_DR)
150 #ifndef CONFIG_DEFAULT_IMMR
151 #error CONFIG_DEFAULT_IMMR must be defined
152 #endif /* CONFIG_SYS_DEFAULT_IMMR */
153 #ifndef CONFIG_SYS_IMMR
154 #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
155 #endif /* CONFIG_SYS_IMMR */
158 * After configuration, a system reset exception is executed using the
159 * vector at offset 0x100 relative to the base set by MSR[IP]. If
160 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
161 * base address is 0xfff00000. In the case of a Power On Reset or Hard
162 * Reset, the value of MSR[IP] is determined by the CIP field in the
165 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
166 * This determines the location of the boot ROM (flash or EPROM) in the
167 * processor's address space at boot time. As long as the HRCW is set up
168 * so that we eventually end up executing the code below when the
169 * processor executes the reset exception, the actual values used should
172 * Once we have got here, the address mask in OR0 is cleared so that the
173 * bottom 32K of the boot ROM is effectively repeated all throughout the
174 * processor's address space, after which we can jump to the absolute
175 * address at which the boot ROM was linked at compile time, and proceed
176 * to initialise the memory controller without worrying if the rug will
177 * be pulled out from under us, so to speak (it will be fine as long as
178 * we configure BR0 with the same boot ROM link address).
180 . = EXC_OFF_SYS_RESET
183 _start: /* time t 0 */
184 lis r4, CONFIG_DEFAULT_IMMR@h
187 mfmsr r5 /* save msr contents */
189 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
193 lis r3, CONFIG_SYS_IMMR@h
194 ori r3, r3, CONFIG_SYS_IMMR@l
200 lwz r6, 0(r7) /* Arbitrary external load */
206 /* Initialise the E300 processor core */
207 /*------------------------------------------*/
209 #ifdef CONFIG_NAND_SPL
210 /* The FCM begins execution after only the first page
211 * is loaded. Wait for the rest before branching
212 * to another flash page.
214 1: lwz r6, 0x50b0(r3)
221 #ifdef CONFIG_SYS_FLASHBOOT
223 /* Inflate flash location so it appears everywhere, calculate */
224 /* the absolute address in final location of the FLASH, jump */
225 /* there and deflate the flash size back to minimal size */
226 /*------------------------------------------------------------*/
228 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
229 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
230 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
234 #if 1 /* Remapping flash with LAW0. */
235 bl remap_flash_by_law0
237 #endif /* CONFIG_SYS_FLASHBOOT */
244 * Cache must be enabled here for stack-in-cache trick.
245 * This means we need to enable the BATS.
247 * 1) for the EVB, original gt regs need to be mapped
248 * 2) need to have an IBAT for the 0xf region,
249 * we are running there!
250 * Cache should be turned on after BATs, since by default
251 * everything is write-through.
252 * The init-mem BAT can be reused after reloc. The old
253 * gt-regs BAT can be reused after board_init_f calls
254 * board_early_init_f (EVB only).
256 /* enable address translation */
260 /* enable the data cache */
263 #ifdef CONFIG_SYS_INIT_RAM_LOCK
268 /* set up the stack pointer in our newly created
270 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
271 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
273 li r0, 0 /* Make room for stack frame header and */
274 stwu r0, -4(r1) /* clear final stack frame so that */
275 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
278 /* let the C-code set up the rest */
280 /* Be careful to keep code relocatable & stack humble */
281 /*------------------------------------------------------*/
283 GET_GOT /* initialize GOT access */
286 lis r3, CONFIG_SYS_IMMR@h
287 /* run low-level CPU init code (in Flash)*/
290 /* run 1st part of board init code (in Flash)*/
293 /* NOTREACHED - board_init_f() does not return */
295 #ifndef CONFIG_NAND_SPL
300 .globl _start_of_vectors
304 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
306 /* Data Storage exception. */
307 STD_EXCEPTION(0x300, DataStorage, UnknownException)
309 /* Instruction Storage exception. */
310 STD_EXCEPTION(0x400, InstStorage, UnknownException)
312 /* External Interrupt exception. */
314 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
317 /* Alignment exception. */
320 EXCEPTION_PROLOG(SRR0, SRR1)
325 addi r3,r1,STACK_FRAME_OVERHEAD
326 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
328 /* Program check exception */
331 EXCEPTION_PROLOG(SRR0, SRR1)
332 addi r3,r1,STACK_FRAME_OVERHEAD
333 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
336 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
338 /* I guess we could implement decrementer, and may have
339 * to someday for timekeeping.
341 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
343 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
344 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
345 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
346 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
348 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
349 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
351 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
352 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
353 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
357 * This exception occurs when the program counter matches the
358 * Instruction Address Breakpoint Register (IABR).
360 * I want the cpu to halt if this occurs so I can hunt around
361 * with the debugger and look at things.
363 * When DEBUG is defined, both machine check enable (in the MSR)
364 * and checkstop reset enable (in the reset mode register) are
365 * turned off and so a checkstop condition will result in the cpu
368 * I force the cpu into a checkstop condition by putting an illegal
369 * instruction here (at least this is the theory).
371 * well - that didnt work, so just do an infinite loop!
375 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
377 STD_EXCEPTION(0x1400, SMI, UnknownException)
379 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
380 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
381 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
382 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
383 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
384 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
385 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
386 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
387 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
388 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
389 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
390 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
391 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
392 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
393 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
394 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
395 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
396 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
397 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
398 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
399 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
400 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
401 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
402 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
403 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
404 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
405 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
408 .globl _end_of_vectors
414 * This code finishes saving the registers to the exception frame
415 * and jumps to the appropriate handler for the exception.
416 * Register r21 is pointer into trap frame, r1 has new stack pointer.
418 .globl transfer_to_handler
429 andi. r24,r23,0x3f00 /* get vector offset */
433 lwz r24,0(r23) /* virtual address of handler */
434 lwz r23,4(r23) /* where to go when done */
439 rfi /* jump to handler, enable MMU */
442 mfmsr r28 /* Disable interrupts */
446 SYNC /* Some chip revs need this... */
461 lwz r2,_NIP(r1) /* Restore environment */
470 #endif /* !CONFIG_NAND_SPL */
473 * This code initialises the E300 processor core
474 * (conforms to PowerPC 603e spec)
475 * Note: expects original MSR contents to be in r5.
477 .globl init_e300_core
478 init_e300_core: /* time t 10 */
479 /* Initialize machine status; enable machine check interrupt */
480 /*-----------------------------------------------------------*/
482 li r3, MSR_KERNEL /* Set ME and RI flags */
483 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
485 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
487 SYNC /* Some chip revs need this... */
490 mtspr SRR1, r3 /* Make SRR1 match MSR */
493 lis r3, CONFIG_SYS_IMMR@h
494 #if defined(CONFIG_WATCHDOG)
495 /* Initialise the Watchdog values and reset it (if req) */
496 /*------------------------------------------------------*/
497 lis r4, CONFIG_SYS_WATCHDOG_VALUE
498 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
508 /* Disable Watchdog */
509 /*-------------------*/
511 /* Check to see if its enabled for disabling
512 once disabled by SW you can't re-enable */
518 #endif /* CONFIG_WATCHDOG */
520 #if defined(CONFIG_MASK_AER_AO)
521 /* Write the Arbiter Event Enable to mask Address Only traps. */
522 /* This prevents the dcbz instruction from being trapped when */
523 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
524 /* COHERENCY bit is set in the WIMG bits, which is often */
525 /* needed for PCI operation. */
527 rlwinm r0, r4, 0, ~AER_AO
529 #endif /* CONFIG_MASK_AER_AO */
531 /* Initialize the Hardware Implementation-dependent Registers */
532 /* HID0 also contains cache control */
533 /* - force invalidation of data and instruction caches */
534 /*------------------------------------------------------*/
536 lis r3, CONFIG_SYS_HID0_INIT@h
537 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
541 lis r3, CONFIG_SYS_HID0_FINAL@h
542 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
546 lis r3, CONFIG_SYS_HID2@h
547 ori r3, r3, CONFIG_SYS_HID2@l
552 /*------------------------------*/
555 /* setup_bats - set them up to some initial state */
561 addis r4, r0, CONFIG_SYS_IBAT0L@h
562 ori r4, r4, CONFIG_SYS_IBAT0L@l
563 addis r3, r0, CONFIG_SYS_IBAT0U@h
564 ori r3, r3, CONFIG_SYS_IBAT0U@l
569 addis r4, r0, CONFIG_SYS_DBAT0L@h
570 ori r4, r4, CONFIG_SYS_DBAT0L@l
571 addis r3, r0, CONFIG_SYS_DBAT0U@h
572 ori r3, r3, CONFIG_SYS_DBAT0U@l
577 addis r4, r0, CONFIG_SYS_IBAT1L@h
578 ori r4, r4, CONFIG_SYS_IBAT1L@l
579 addis r3, r0, CONFIG_SYS_IBAT1U@h
580 ori r3, r3, CONFIG_SYS_IBAT1U@l
585 addis r4, r0, CONFIG_SYS_DBAT1L@h
586 ori r4, r4, CONFIG_SYS_DBAT1L@l
587 addis r3, r0, CONFIG_SYS_DBAT1U@h
588 ori r3, r3, CONFIG_SYS_DBAT1U@l
593 addis r4, r0, CONFIG_SYS_IBAT2L@h
594 ori r4, r4, CONFIG_SYS_IBAT2L@l
595 addis r3, r0, CONFIG_SYS_IBAT2U@h
596 ori r3, r3, CONFIG_SYS_IBAT2U@l
601 addis r4, r0, CONFIG_SYS_DBAT2L@h
602 ori r4, r4, CONFIG_SYS_DBAT2L@l
603 addis r3, r0, CONFIG_SYS_DBAT2U@h
604 ori r3, r3, CONFIG_SYS_DBAT2U@l
609 addis r4, r0, CONFIG_SYS_IBAT3L@h
610 ori r4, r4, CONFIG_SYS_IBAT3L@l
611 addis r3, r0, CONFIG_SYS_IBAT3U@h
612 ori r3, r3, CONFIG_SYS_IBAT3U@l
617 addis r4, r0, CONFIG_SYS_DBAT3L@h
618 ori r4, r4, CONFIG_SYS_DBAT3L@l
619 addis r3, r0, CONFIG_SYS_DBAT3U@h
620 ori r3, r3, CONFIG_SYS_DBAT3U@l
624 #ifdef CONFIG_HIGH_BATS
626 addis r4, r0, CONFIG_SYS_IBAT4L@h
627 ori r4, r4, CONFIG_SYS_IBAT4L@l
628 addis r3, r0, CONFIG_SYS_IBAT4U@h
629 ori r3, r3, CONFIG_SYS_IBAT4U@l
634 addis r4, r0, CONFIG_SYS_DBAT4L@h
635 ori r4, r4, CONFIG_SYS_DBAT4L@l
636 addis r3, r0, CONFIG_SYS_DBAT4U@h
637 ori r3, r3, CONFIG_SYS_DBAT4U@l
642 addis r4, r0, CONFIG_SYS_IBAT5L@h
643 ori r4, r4, CONFIG_SYS_IBAT5L@l
644 addis r3, r0, CONFIG_SYS_IBAT5U@h
645 ori r3, r3, CONFIG_SYS_IBAT5U@l
650 addis r4, r0, CONFIG_SYS_DBAT5L@h
651 ori r4, r4, CONFIG_SYS_DBAT5L@l
652 addis r3, r0, CONFIG_SYS_DBAT5U@h
653 ori r3, r3, CONFIG_SYS_DBAT5U@l
658 addis r4, r0, CONFIG_SYS_IBAT6L@h
659 ori r4, r4, CONFIG_SYS_IBAT6L@l
660 addis r3, r0, CONFIG_SYS_IBAT6U@h
661 ori r3, r3, CONFIG_SYS_IBAT6U@l
666 addis r4, r0, CONFIG_SYS_DBAT6L@h
667 ori r4, r4, CONFIG_SYS_DBAT6L@l
668 addis r3, r0, CONFIG_SYS_DBAT6U@h
669 ori r3, r3, CONFIG_SYS_DBAT6U@l
674 addis r4, r0, CONFIG_SYS_IBAT7L@h
675 ori r4, r4, CONFIG_SYS_IBAT7L@l
676 addis r3, r0, CONFIG_SYS_IBAT7U@h
677 ori r3, r3, CONFIG_SYS_IBAT7U@l
682 addis r4, r0, CONFIG_SYS_DBAT7L@h
683 ori r4, r4, CONFIG_SYS_DBAT7L@l
684 addis r3, r0, CONFIG_SYS_DBAT7U@h
685 ori r3, r3, CONFIG_SYS_DBAT7U@l
692 /* invalidate all tlb's
694 * From the 603e User Manual: "The 603e provides the ability to
695 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
696 * instruction invalidates the TLB entry indexed by the EA, and
697 * operates on both the instruction and data TLBs simultaneously
698 * invalidating four TLB entries (both sets in each TLB). The
699 * index corresponds to bits 15-19 of the EA. To invalidate all
700 * entries within both TLBs, 32 tlbie instructions should be
701 * issued, incrementing this field by one each time."
703 * "Note that the tlbia instruction is not implemented on the
706 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
707 * incrementing by 0x1000 each time. The code below is sort of
708 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
724 * Note: requires that all cache bits in
725 * HID0 are in the low half word.
727 #ifndef CONFIG_NAND_SPL
732 li r4, HID0_ICFI|HID0_ILOCK
734 ori r4, r3, HID0_ICFI
736 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
738 mtspr HID0, r3 /* clears invalidate */
741 .globl icache_disable
745 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
748 mtspr HID0, r3 /* clears invalidate, enable and lock */
754 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
756 #endif /* !CONFIG_NAND_SPL */
761 li r5, HID0_DCFI|HID0_DLOCK
765 mtspr HID0, r3 /* enable, no invalidate */
768 .globl dcache_disable
771 bl flush_dcache /* uses r3 and r5 */
773 li r5, HID0_DCE|HID0_DLOCK
775 ori r5, r3, HID0_DCFI
777 mtspr HID0, r5 /* sets invalidate, clears enable and lock */
779 mtspr HID0, r3 /* clears invalidate */
786 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
792 lis r5, CONFIG_SYS_CACHELINE_SIZE
796 lis r5, CONFIG_SYS_CACHELINE_SIZE
801 /*-------------------------------------------------------------------*/
804 * void relocate_code (addr_sp, gd, addr_moni)
806 * This "function" does not return, instead it continues in RAM
807 * after relocating the monitor code.
811 * r5 = length in bytes
816 mr r1, r3 /* Set new stack pointer */
817 mr r9, r4 /* Save copy of Global Data pointer */
818 mr r10, r5 /* Save copy of Destination Address */
821 mr r3, r5 /* Destination Address */
822 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
823 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
824 lwz r5, GOT(__bss_start)
826 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
831 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
832 * + Destination Address
838 /* First our own GOT */
840 /* then the one used by the C code */
850 beq cr1,4f /* In place copy is not necessary */
851 beq 7f /* Protect against 0 count */
880 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
888 * Now flush the cache: note that we must start from a cache aligned
889 * address. Otherwise we might miss one cache line.
893 beq 7f /* Always flush prefetch queue in any case */
901 sync /* Wait for all dcbst to complete on bus */
907 7: sync /* Wait for all icbi to complete on bus */
911 * We are done. Do not return, instead branch to second part of board
912 * initialization, now running from RAM.
914 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
921 * Relocation Function, r12 point to got2+0x8000
923 * Adjust got2 pointers, no need to check for 0, this code
924 * already puts a few entries in the table.
926 li r0,__got2_entries@sectoff@l
927 la r3,GOT(_GOT2_TABLE_)
928 lwz r11,GOT(_GOT2_TABLE_)
939 #ifndef CONFIG_NAND_SPL
941 * Now adjust the fixups and the pointers to the fixups
942 * in case we need to move ourselves again.
944 li r0,__fixup_entries@sectoff@l
945 lwz r3,GOT(_FIXUP_TABLE_)
963 * Now clear BSS segment
965 lwz r3,GOT(__bss_start)
966 #if defined(CONFIG_HYMOD)
968 * For HYMOD - the environment is the very last item in flash.
969 * The real .bss stops just before environment starts, so only
970 * clear up to that point.
972 * taken from mods for FADS board
974 lwz r4,GOT(environment)
976 lwz r4,GOT(__bss_end__)
990 mr r3, r9 /* Global Data pointer */
991 mr r4, r10 /* Destination Address */
994 #ifndef CONFIG_NAND_SPL
996 * Copy exception vector code to low memory
999 * r7: source address, r8: end address, r9: target address
1003 mflr r4 /* save link register */
1006 lwz r8, GOT(_end_of_vectors)
1008 li r9, 0x100 /* reset vector always at 0x100 */
1011 bgelr /* return if r7>=r8 - just in case */
1021 * relocate `hdlr' and `int_return' entries
1023 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1024 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1027 addi r7, r7, 0x100 /* next exception vector */
1031 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1034 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1037 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1038 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1041 addi r7, r7, 0x100 /* next exception vector */
1045 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1046 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1049 addi r7, r7, 0x100 /* next exception vector */
1053 mfmsr r3 /* now that the vectors have */
1054 lis r7, MSR_IP@h /* relocated into low memory */
1055 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1056 andc r3, r3, r7 /* (if it was on) */
1057 SYNC /* Some chip revs need this... */
1061 mtlr r4 /* restore link register */
1064 #endif /* !CONFIG_NAND_SPL */
1066 #ifdef CONFIG_SYS_INIT_RAM_LOCK
1068 /* Allocate Initial RAM in data cache.
1070 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1071 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1072 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
1073 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1080 /* Lock the data cache */
1082 ori r0, r0, HID0_DLOCK
1088 #ifndef CONFIG_NAND_SPL
1089 .globl unlock_ram_in_cache
1090 unlock_ram_in_cache:
1091 /* invalidate the INIT_RAM section */
1092 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1093 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1094 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
1095 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1101 sync /* Wait for all icbi to complete on bus */
1104 /* Unlock the data cache and invalidate it */
1106 li r5, HID0_DLOCK|HID0_DCFI
1107 andc r3, r3, r5 /* no invalidate, unlock */
1108 ori r5, r3, HID0_DCFI /* invalidate, unlock */
1110 mtspr HID0, r5 /* invalidate, unlock */
1112 mtspr HID0, r3 /* no invalidate, unlock */
1114 #endif /* !CONFIG_NAND_SPL */
1115 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
1117 #ifdef CONFIG_SYS_FLASHBOOT
1119 /* When booting from ROM (Flash or EPROM), clear the */
1120 /* Address Mask in OR0 so ROM appears everywhere */
1121 /*----------------------------------------------------*/
1122 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
1124 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1126 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1128 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1129 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1130 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1131 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1132 * 0xFF800. From the hard resetting to here, the processor fetched and
1133 * executed the instructions one by one. There is not absolutely
1134 * jumping happened. Laterly, the u-boot code has to do an absolutely
1135 * jumping to tell the CPU instruction fetching component what the
1136 * u-boot TEXT base address is. Because the TEXT base resides in the
1137 * boot ROM memory space, to garantee the code can run smoothly after
1138 * that jumping, we must map in the entire boot ROM by Local Access
1139 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1140 * address for boot ROM, such as 0xFE000000. In this case, the default
1141 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1142 * need another window to map in it.
1144 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1145 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1146 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
1148 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
1149 lis r4, (0x80000012)@h
1150 ori r4, r4, (0x80000012)@l
1151 li r5, CONFIG_SYS_FLASH_SIZE
1152 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1156 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1157 /* Wait for HW to catch up */
1158 lwz r4, LBLAWAR1(r3)
1163 /* Though all the LBIU Local Access Windows and LBC Banks will be
1164 * initialized in the C code, we'd better configure boot ROM's
1165 * window 0 and bank 0 correctly at here.
1167 remap_flash_by_law0:
1168 /* Initialize the BR0 with the boot ROM starting address. */
1172 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1173 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
1175 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1178 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
1182 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1183 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1184 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
1186 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
1187 lis r4, (0x80000012)@h
1188 ori r4, r4, (0x80000012)@l
1189 li r5, CONFIG_SYS_FLASH_SIZE
1190 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1193 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1197 stw r4, LBLAWBAR1(r3)
1198 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
1199 /* Wait for HW to catch up */
1200 lwz r4, LBLAWAR1(r3)
1204 #endif /* CONFIG_SYS_FLASHBOOT */