8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
24 config TARGET_SOCRATES
25 bool "Support socrates"
28 config TARGET_B4420QDS
29 bool "Support B4420QDS"
34 config TARGET_B4860QDS
35 bool "Support B4860QDS"
37 select BOARD_LATE_INIT if CHAIN_OF_TRUST
41 config TARGET_BSC9131RDB
42 bool "Support BSC9131RDB"
45 select BOARD_EARLY_INIT_F
47 config TARGET_BSC9132QDS
48 bool "Support BSC9132QDS"
50 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 select BOARD_EARLY_INIT_F
54 config TARGET_C29XPCIE
55 bool "Support C29XPCIE"
57 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 bool "Support P3041DS"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
70 bool "Support P4080DS"
73 select BOARD_LATE_INIT if CHAIN_OF_TRUST
77 bool "Support P5020DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
84 bool "Support P5040DS"
87 select BOARD_LATE_INIT if CHAIN_OF_TRUST
90 config TARGET_MPC8536DS
91 bool "Support MPC8536DS"
93 # Use DDR3 controller with DDR2 DIMMs on this board
94 select SYS_FSL_DDRC_GEN3
97 config TARGET_MPC8541CDS
98 bool "Support MPC8541CDS"
101 config TARGET_MPC8544DS
102 bool "Support MPC8544DS"
105 config TARGET_MPC8548CDS
106 bool "Support MPC8548CDS"
108 imply ENV_IS_IN_FLASH
110 config TARGET_MPC8555CDS
111 bool "Support MPC8555CDS"
114 config TARGET_MPC8568MDS
115 bool "Support MPC8568MDS"
118 config TARGET_MPC8569MDS
119 bool "Support MPC8569MDS"
122 config TARGET_MPC8572DS
123 bool "Support MPC8572DS"
125 # Use DDR3 controller with DDR2 DIMMs on this board
126 select SYS_FSL_DDRC_GEN3
129 config TARGET_P1010RDB_PA
130 bool "Support P1010RDB_PA"
132 select BOARD_LATE_INIT if CHAIN_OF_TRUST
138 config TARGET_P1010RDB_PB
139 bool "Support P1010RDB_PB"
141 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_P1022DS
148 bool "Support P1022DS"
154 config TARGET_P1023RDB
155 bool "Support P1023RDB"
159 config TARGET_P1020MBG
160 bool "Support P1020MBG-PC"
167 config TARGET_P1020RDB_PC
168 bool "Support P1020RDB-PC"
175 config TARGET_P1020RDB_PD
176 bool "Support P1020RDB-PD"
183 config TARGET_P1020UTM
184 bool "Support P1020UTM"
191 config TARGET_P1021RDB
192 bool "Support P1021RDB"
199 config TARGET_P1024RDB
200 bool "Support P1024RDB"
207 config TARGET_P1025RDB
208 bool "Support P1025RDB"
215 config TARGET_P2020RDB
216 bool "Support P2020RDB-PC"
224 bool "Support p1_twr"
227 config TARGET_P2041RDB
228 bool "Support P2041RDB"
230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
234 config TARGET_QEMU_PPCE500
235 bool "Support qemu-ppce500"
236 select ARCH_QEMU_E500
239 config TARGET_T1024QDS
240 bool "Support T1024QDS"
242 select BOARD_LATE_INIT if CHAIN_OF_TRUST
248 config TARGET_T1023RDB
249 bool "Support T1023RDB"
251 select BOARD_LATE_INIT if CHAIN_OF_TRUST
256 config TARGET_T1024RDB
257 bool "Support T1024RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
264 config TARGET_T1040QDS
265 bool "Support T1040QDS"
267 select BOARD_LATE_INIT if CHAIN_OF_TRUST
272 config TARGET_T1040RDB
273 bool "Support T1040RDB"
275 select BOARD_LATE_INIT if CHAIN_OF_TRUST
280 config TARGET_T1040D4RDB
281 bool "Support T1040D4RDB"
283 select BOARD_LATE_INIT if CHAIN_OF_TRUST
288 config TARGET_T1042RDB
289 bool "Support T1042RDB"
291 select BOARD_LATE_INIT if CHAIN_OF_TRUST
296 config TARGET_T1042D4RDB
297 bool "Support T1042D4RDB"
299 select BOARD_LATE_INIT if CHAIN_OF_TRUST
304 config TARGET_T1042RDB_PI
305 bool "Support T1042RDB_PI"
307 select BOARD_LATE_INIT if CHAIN_OF_TRUST
312 config TARGET_T2080QDS
313 bool "Support T2080QDS"
315 select BOARD_LATE_INIT if CHAIN_OF_TRUST
320 config TARGET_T2080RDB
321 bool "Support T2080RDB"
323 select BOARD_LATE_INIT if CHAIN_OF_TRUST
328 config TARGET_T2081QDS
329 bool "Support T2081QDS"
334 config TARGET_T4160QDS
335 bool "Support T4160QDS"
337 select BOARD_LATE_INIT if CHAIN_OF_TRUST
342 config TARGET_T4160RDB
343 bool "Support T4160RDB"
348 config TARGET_T4240QDS
349 bool "Support T4240QDS"
351 select BOARD_LATE_INIT if CHAIN_OF_TRUST
356 config TARGET_T4240RDB
357 bool "Support T4240RDB"
363 config TARGET_CONTROLCENTERD
364 bool "Support controlcenterd"
367 config TARGET_KMP204X
368 bool "Support kmp204x"
374 config TARGET_XPEDITE520X
375 bool "Support xpedite520x"
378 config TARGET_XPEDITE537X
379 bool "Support xpedite537x"
381 # Use DDR3 controller with DDR2 DIMMs on this board
382 select SYS_FSL_DDRC_GEN3
384 config TARGET_XPEDITE550X
385 bool "Support xpedite550x"
388 config TARGET_UCP1020
389 bool "Support uCP1020"
393 config TARGET_CYRUS_P5020
394 bool "Support Varisys Cyrus P5020"
398 config TARGET_CYRUS_P5040
399 bool "Support Varisys Cyrus P5040"
410 select SYS_FSL_DDR_VER_47
411 select SYS_FSL_ERRATUM_A004477
412 select SYS_FSL_ERRATUM_A005871
413 select SYS_FSL_ERRATUM_A006379
414 select SYS_FSL_ERRATUM_A006384
415 select SYS_FSL_ERRATUM_A006475
416 select SYS_FSL_ERRATUM_A006593
417 select SYS_FSL_ERRATUM_A007075
418 select SYS_FSL_ERRATUM_A007186
419 select SYS_FSL_ERRATUM_A007212
420 select SYS_FSL_ERRATUM_A009942
421 select SYS_FSL_HAS_DDR3
422 select SYS_FSL_HAS_SEC
423 select SYS_FSL_QORIQ_CHASSIS2
424 select SYS_FSL_SEC_BE
425 select SYS_FSL_SEC_COMPAT_4
436 select SYS_FSL_DDR_VER_47
437 select SYS_FSL_ERRATUM_A004477
438 select SYS_FSL_ERRATUM_A005871
439 select SYS_FSL_ERRATUM_A006379
440 select SYS_FSL_ERRATUM_A006384
441 select SYS_FSL_ERRATUM_A006475
442 select SYS_FSL_ERRATUM_A006593
443 select SYS_FSL_ERRATUM_A007075
444 select SYS_FSL_ERRATUM_A007186
445 select SYS_FSL_ERRATUM_A007212
446 select SYS_FSL_ERRATUM_A007907
447 select SYS_FSL_ERRATUM_A009942
448 select SYS_FSL_HAS_DDR3
449 select SYS_FSL_HAS_SEC
450 select SYS_FSL_QORIQ_CHASSIS2
451 select SYS_FSL_SEC_BE
452 select SYS_FSL_SEC_COMPAT_4
461 select SYS_FSL_DDR_VER_44
462 select SYS_FSL_ERRATUM_A004477
463 select SYS_FSL_ERRATUM_A005125
464 select SYS_FSL_ERRATUM_ESDHC111
465 select SYS_FSL_HAS_DDR3
466 select SYS_FSL_HAS_SEC
467 select SYS_FSL_SEC_BE
468 select SYS_FSL_SEC_COMPAT_4
476 select SYS_FSL_DDR_VER_46
477 select SYS_FSL_ERRATUM_A004477
478 select SYS_FSL_ERRATUM_A005125
479 select SYS_FSL_ERRATUM_A005434
480 select SYS_FSL_ERRATUM_ESDHC111
481 select SYS_FSL_ERRATUM_I2C_A004447
482 select SYS_FSL_ERRATUM_IFC_A002769
483 select SYS_FSL_HAS_DDR3
484 select SYS_FSL_HAS_SEC
485 select SYS_FSL_SEC_BE
486 select SYS_FSL_SEC_COMPAT_4
487 select SYS_PPC_E500_USE_DEBUG_TLB
497 select SYS_FSL_DDR_VER_46
498 select SYS_FSL_ERRATUM_A005125
499 select SYS_FSL_ERRATUM_ESDHC111
500 select SYS_FSL_HAS_DDR3
501 select SYS_FSL_HAS_SEC
502 select SYS_FSL_SEC_BE
503 select SYS_FSL_SEC_COMPAT_6
504 select SYS_PPC_E500_USE_DEBUG_TLB
512 select SYS_FSL_ERRATUM_A004508
513 select SYS_FSL_ERRATUM_A005125
514 select SYS_FSL_HAS_DDR2
515 select SYS_FSL_HAS_DDR3
516 select SYS_FSL_HAS_SEC
517 select SYS_FSL_SEC_BE
518 select SYS_FSL_SEC_COMPAT_2
519 select SYS_PPC_E500_USE_DEBUG_TLB
527 select SYS_FSL_HAS_DDR1
532 select SYS_FSL_HAS_DDR1
533 select SYS_FSL_HAS_SEC
534 select SYS_FSL_SEC_BE
535 select SYS_FSL_SEC_COMPAT_2
540 select SYS_FSL_ERRATUM_A005125
541 select SYS_FSL_HAS_DDR2
542 select SYS_FSL_HAS_SEC
543 select SYS_FSL_SEC_BE
544 select SYS_FSL_SEC_COMPAT_2
545 select SYS_PPC_E500_USE_DEBUG_TLB
551 select SYS_FSL_ERRATUM_A005125
552 select SYS_FSL_ERRATUM_NMG_DDR120
553 select SYS_FSL_ERRATUM_NMG_LBC103
554 select SYS_FSL_ERRATUM_NMG_ETSEC129
555 select SYS_FSL_ERRATUM_I2C_A004447
556 select SYS_FSL_HAS_DDR2
557 select SYS_FSL_HAS_DDR1
558 select SYS_FSL_HAS_SEC
559 select SYS_FSL_SEC_BE
560 select SYS_FSL_SEC_COMPAT_2
561 select SYS_PPC_E500_USE_DEBUG_TLB
562 imply ENV_IS_IN_FLASH
567 select SYS_FSL_HAS_DDR1
568 select SYS_FSL_HAS_SEC
569 select SYS_FSL_SEC_BE
570 select SYS_FSL_SEC_COMPAT_2
575 select SYS_FSL_HAS_DDR1
580 select SYS_FSL_HAS_DDR2
581 select SYS_FSL_HAS_SEC
582 select SYS_FSL_SEC_BE
583 select SYS_FSL_SEC_COMPAT_2
588 select SYS_FSL_ERRATUM_A004508
589 select SYS_FSL_ERRATUM_A005125
590 select SYS_FSL_HAS_DDR3
591 select SYS_FSL_HAS_SEC
592 select SYS_FSL_SEC_BE
593 select SYS_FSL_SEC_COMPAT_2
600 select SYS_FSL_ERRATUM_A004508
601 select SYS_FSL_ERRATUM_A005125
602 select SYS_FSL_ERRATUM_DDR_115
603 select SYS_FSL_ERRATUM_DDR111_DDR134
604 select SYS_FSL_HAS_DDR2
605 select SYS_FSL_HAS_DDR3
606 select SYS_FSL_HAS_SEC
607 select SYS_FSL_SEC_BE
608 select SYS_FSL_SEC_COMPAT_2
609 select SYS_PPC_E500_USE_DEBUG_TLB
612 imply ENV_IS_IN_FLASH
617 select SYS_FSL_ERRATUM_A004477
618 select SYS_FSL_ERRATUM_A004508
619 select SYS_FSL_ERRATUM_A005125
620 select SYS_FSL_ERRATUM_A006261
621 select SYS_FSL_ERRATUM_A007075
622 select SYS_FSL_ERRATUM_ESDHC111
623 select SYS_FSL_ERRATUM_I2C_A004447
624 select SYS_FSL_ERRATUM_IFC_A002769
625 select SYS_FSL_ERRATUM_P1010_A003549
626 select SYS_FSL_ERRATUM_SEC_A003571
627 select SYS_FSL_ERRATUM_IFC_A003399
628 select SYS_FSL_HAS_DDR3
629 select SYS_FSL_HAS_SEC
630 select SYS_FSL_SEC_BE
631 select SYS_FSL_SEC_COMPAT_4
632 select SYS_PPC_E500_USE_DEBUG_TLB
643 select SYS_FSL_ERRATUM_A004508
644 select SYS_FSL_ERRATUM_A005125
645 select SYS_FSL_ERRATUM_ELBC_A001
646 select SYS_FSL_ERRATUM_ESDHC111
647 select SYS_FSL_HAS_DDR3
648 select SYS_FSL_HAS_SEC
649 select SYS_FSL_SEC_BE
650 select SYS_FSL_SEC_COMPAT_2
651 select SYS_PPC_E500_USE_DEBUG_TLB
657 select SYS_FSL_ERRATUM_A004508
658 select SYS_FSL_ERRATUM_A005125
659 select SYS_FSL_ERRATUM_ELBC_A001
660 select SYS_FSL_ERRATUM_ESDHC111
661 select SYS_FSL_HAS_DDR3
662 select SYS_FSL_HAS_SEC
663 select SYS_FSL_SEC_BE
664 select SYS_FSL_SEC_COMPAT_2
665 select SYS_PPC_E500_USE_DEBUG_TLB
674 select SYS_FSL_ERRATUM_A004508
675 select SYS_FSL_ERRATUM_A005125
676 select SYS_FSL_ERRATUM_ELBC_A001
677 select SYS_FSL_ERRATUM_ESDHC111
678 select SYS_FSL_HAS_DDR3
679 select SYS_FSL_HAS_SEC
680 select SYS_FSL_SEC_BE
681 select SYS_FSL_SEC_COMPAT_2
682 select SYS_PPC_E500_USE_DEBUG_TLB
690 select SYS_FSL_ERRATUM_A004477
691 select SYS_FSL_ERRATUM_A004508
692 select SYS_FSL_ERRATUM_A005125
693 select SYS_FSL_ERRATUM_ELBC_A001
694 select SYS_FSL_ERRATUM_ESDHC111
695 select SYS_FSL_ERRATUM_SATA_A001
696 select SYS_FSL_HAS_DDR3
697 select SYS_FSL_HAS_SEC
698 select SYS_FSL_SEC_BE
699 select SYS_FSL_SEC_COMPAT_2
700 select SYS_PPC_E500_USE_DEBUG_TLB
706 select SYS_FSL_ERRATUM_A004508
707 select SYS_FSL_ERRATUM_A005125
708 select SYS_FSL_ERRATUM_I2C_A004447
709 select SYS_FSL_HAS_DDR3
710 select SYS_FSL_HAS_SEC
711 select SYS_FSL_SEC_BE
712 select SYS_FSL_SEC_COMPAT_4
718 select SYS_FSL_ERRATUM_A004508
719 select SYS_FSL_ERRATUM_A005125
720 select SYS_FSL_ERRATUM_ELBC_A001
721 select SYS_FSL_ERRATUM_ESDHC111
722 select SYS_FSL_HAS_DDR3
723 select SYS_FSL_HAS_SEC
724 select SYS_FSL_SEC_BE
725 select SYS_FSL_SEC_COMPAT_2
726 select SYS_PPC_E500_USE_DEBUG_TLB
736 select SYS_FSL_ERRATUM_A004508
737 select SYS_FSL_ERRATUM_A005125
738 select SYS_FSL_ERRATUM_ELBC_A001
739 select SYS_FSL_ERRATUM_ESDHC111
740 select SYS_FSL_HAS_DDR3
741 select SYS_FSL_HAS_SEC
742 select SYS_FSL_SEC_BE
743 select SYS_FSL_SEC_COMPAT_2
744 select SYS_PPC_E500_USE_DEBUG_TLB
751 select SYS_FSL_ERRATUM_A004477
752 select SYS_FSL_ERRATUM_A004508
753 select SYS_FSL_ERRATUM_A005125
754 select SYS_FSL_ERRATUM_ESDHC111
755 select SYS_FSL_ERRATUM_ESDHC_A001
756 select SYS_FSL_HAS_DDR3
757 select SYS_FSL_HAS_SEC
758 select SYS_FSL_SEC_BE
759 select SYS_FSL_SEC_COMPAT_2
760 select SYS_PPC_E500_USE_DEBUG_TLB
769 select SYS_FSL_ERRATUM_A004510
770 select SYS_FSL_ERRATUM_A004849
771 select SYS_FSL_ERRATUM_A006261
772 select SYS_FSL_ERRATUM_CPU_A003999
773 select SYS_FSL_ERRATUM_DDR_A003
774 select SYS_FSL_ERRATUM_DDR_A003474
775 select SYS_FSL_ERRATUM_ESDHC111
776 select SYS_FSL_ERRATUM_I2C_A004447
777 select SYS_FSL_ERRATUM_NMG_CPU_A011
778 select SYS_FSL_ERRATUM_SRIO_A004034
779 select SYS_FSL_ERRATUM_USB14
780 select SYS_FSL_HAS_DDR3
781 select SYS_FSL_HAS_SEC
782 select SYS_FSL_QORIQ_CHASSIS1
783 select SYS_FSL_SEC_BE
784 select SYS_FSL_SEC_COMPAT_4
792 select SYS_FSL_DDR_VER_44
793 select SYS_FSL_ERRATUM_A004510
794 select SYS_FSL_ERRATUM_A004849
795 select SYS_FSL_ERRATUM_A005812
796 select SYS_FSL_ERRATUM_A006261
797 select SYS_FSL_ERRATUM_CPU_A003999
798 select SYS_FSL_ERRATUM_DDR_A003
799 select SYS_FSL_ERRATUM_DDR_A003474
800 select SYS_FSL_ERRATUM_ESDHC111
801 select SYS_FSL_ERRATUM_I2C_A004447
802 select SYS_FSL_ERRATUM_NMG_CPU_A011
803 select SYS_FSL_ERRATUM_SRIO_A004034
804 select SYS_FSL_ERRATUM_USB14
805 select SYS_FSL_HAS_DDR3
806 select SYS_FSL_HAS_SEC
807 select SYS_FSL_QORIQ_CHASSIS1
808 select SYS_FSL_SEC_BE
809 select SYS_FSL_SEC_COMPAT_4
818 select SYS_FSL_DDR_VER_44
819 select SYS_FSL_ERRATUM_A004510
820 select SYS_FSL_ERRATUM_A004580
821 select SYS_FSL_ERRATUM_A004849
822 select SYS_FSL_ERRATUM_A005812
823 select SYS_FSL_ERRATUM_A007075
824 select SYS_FSL_ERRATUM_CPC_A002
825 select SYS_FSL_ERRATUM_CPC_A003
826 select SYS_FSL_ERRATUM_CPU_A003999
827 select SYS_FSL_ERRATUM_DDR_A003
828 select SYS_FSL_ERRATUM_DDR_A003474
829 select SYS_FSL_ERRATUM_ELBC_A001
830 select SYS_FSL_ERRATUM_ESDHC111
831 select SYS_FSL_ERRATUM_ESDHC13
832 select SYS_FSL_ERRATUM_ESDHC135
833 select SYS_FSL_ERRATUM_I2C_A004447
834 select SYS_FSL_ERRATUM_NMG_CPU_A011
835 select SYS_FSL_ERRATUM_SRIO_A004034
836 select SYS_P4080_ERRATUM_CPU22
837 select SYS_P4080_ERRATUM_PCIE_A003
838 select SYS_P4080_ERRATUM_SERDES8
839 select SYS_P4080_ERRATUM_SERDES9
840 select SYS_P4080_ERRATUM_SERDES_A001
841 select SYS_P4080_ERRATUM_SERDES_A005
842 select SYS_FSL_HAS_DDR3
843 select SYS_FSL_HAS_SEC
844 select SYS_FSL_QORIQ_CHASSIS1
845 select SYS_FSL_SEC_BE
846 select SYS_FSL_SEC_COMPAT_4
854 select SYS_FSL_DDR_VER_44
855 select SYS_FSL_ERRATUM_A004510
856 select SYS_FSL_ERRATUM_A006261
857 select SYS_FSL_ERRATUM_DDR_A003
858 select SYS_FSL_ERRATUM_DDR_A003474
859 select SYS_FSL_ERRATUM_ESDHC111
860 select SYS_FSL_ERRATUM_I2C_A004447
861 select SYS_FSL_ERRATUM_SRIO_A004034
862 select SYS_FSL_ERRATUM_USB14
863 select SYS_FSL_HAS_DDR3
864 select SYS_FSL_HAS_SEC
865 select SYS_FSL_QORIQ_CHASSIS1
866 select SYS_FSL_SEC_BE
867 select SYS_FSL_SEC_COMPAT_4
876 select SYS_FSL_DDR_VER_44
877 select SYS_FSL_ERRATUM_A004510
878 select SYS_FSL_ERRATUM_A004699
879 select SYS_FSL_ERRATUM_A005812
880 select SYS_FSL_ERRATUM_A006261
881 select SYS_FSL_ERRATUM_DDR_A003
882 select SYS_FSL_ERRATUM_DDR_A003474
883 select SYS_FSL_ERRATUM_ESDHC111
884 select SYS_FSL_ERRATUM_USB14
885 select SYS_FSL_HAS_DDR3
886 select SYS_FSL_HAS_SEC
887 select SYS_FSL_QORIQ_CHASSIS1
888 select SYS_FSL_SEC_BE
889 select SYS_FSL_SEC_COMPAT_4
894 config ARCH_QEMU_E500
901 select SYS_FSL_DDR_VER_50
902 select SYS_FSL_ERRATUM_A008378
903 select SYS_FSL_ERRATUM_A009663
904 select SYS_FSL_ERRATUM_A009942
905 select SYS_FSL_ERRATUM_ESDHC111
906 select SYS_FSL_HAS_DDR3
907 select SYS_FSL_HAS_DDR4
908 select SYS_FSL_HAS_SEC
909 select SYS_FSL_QORIQ_CHASSIS2
910 select SYS_FSL_SEC_BE
911 select SYS_FSL_SEC_COMPAT_5
920 select SYS_FSL_DDR_VER_50
921 select SYS_FSL_ERRATUM_A008378
922 select SYS_FSL_ERRATUM_A009663
923 select SYS_FSL_ERRATUM_A009942
924 select SYS_FSL_ERRATUM_ESDHC111
925 select SYS_FSL_HAS_DDR3
926 select SYS_FSL_HAS_DDR4
927 select SYS_FSL_HAS_SEC
928 select SYS_FSL_QORIQ_CHASSIS2
929 select SYS_FSL_SEC_BE
930 select SYS_FSL_SEC_COMPAT_5
940 select SYS_FSL_DDR_VER_50
941 select SYS_FSL_ERRATUM_A008044
942 select SYS_FSL_ERRATUM_A008378
943 select SYS_FSL_ERRATUM_A009663
944 select SYS_FSL_ERRATUM_A009942
945 select SYS_FSL_ERRATUM_ESDHC111
946 select SYS_FSL_HAS_DDR3
947 select SYS_FSL_HAS_DDR4
948 select SYS_FSL_HAS_SEC
949 select SYS_FSL_QORIQ_CHASSIS2
950 select SYS_FSL_SEC_BE
951 select SYS_FSL_SEC_COMPAT_5
961 select SYS_FSL_DDR_VER_50
962 select SYS_FSL_ERRATUM_A008044
963 select SYS_FSL_ERRATUM_A008378
964 select SYS_FSL_ERRATUM_A009663
965 select SYS_FSL_ERRATUM_A009942
966 select SYS_FSL_ERRATUM_ESDHC111
967 select SYS_FSL_HAS_DDR3
968 select SYS_FSL_HAS_DDR4
969 select SYS_FSL_HAS_SEC
970 select SYS_FSL_QORIQ_CHASSIS2
971 select SYS_FSL_SEC_BE
972 select SYS_FSL_SEC_COMPAT_5
983 select SYS_FSL_DDR_VER_47
984 select SYS_FSL_ERRATUM_A006379
985 select SYS_FSL_ERRATUM_A006593
986 select SYS_FSL_ERRATUM_A007186
987 select SYS_FSL_ERRATUM_A007212
988 select SYS_FSL_ERRATUM_A007815
989 select SYS_FSL_ERRATUM_A007907
990 select SYS_FSL_ERRATUM_A009942
991 select SYS_FSL_ERRATUM_ESDHC111
992 select SYS_FSL_HAS_DDR3
993 select SYS_FSL_HAS_SEC
994 select SYS_FSL_QORIQ_CHASSIS2
995 select SYS_FSL_SEC_BE
996 select SYS_FSL_SEC_COMPAT_4
1007 select SYS_FSL_DDR_VER_47
1008 select SYS_FSL_ERRATUM_A006379
1009 select SYS_FSL_ERRATUM_A006593
1010 select SYS_FSL_ERRATUM_A007186
1011 select SYS_FSL_ERRATUM_A007212
1012 select SYS_FSL_ERRATUM_A009942
1013 select SYS_FSL_ERRATUM_ESDHC111
1014 select SYS_FSL_HAS_DDR3
1015 select SYS_FSL_HAS_SEC
1016 select SYS_FSL_QORIQ_CHASSIS2
1017 select SYS_FSL_SEC_BE
1018 select SYS_FSL_SEC_COMPAT_4
1028 select SYS_FSL_DDR_VER_47
1029 select SYS_FSL_ERRATUM_A004468
1030 select SYS_FSL_ERRATUM_A005871
1031 select SYS_FSL_ERRATUM_A006379
1032 select SYS_FSL_ERRATUM_A006593
1033 select SYS_FSL_ERRATUM_A007186
1034 select SYS_FSL_ERRATUM_A007798
1035 select SYS_FSL_ERRATUM_A009942
1036 select SYS_FSL_HAS_DDR3
1037 select SYS_FSL_HAS_SEC
1038 select SYS_FSL_QORIQ_CHASSIS2
1039 select SYS_FSL_SEC_BE
1040 select SYS_FSL_SEC_COMPAT_4
1051 select SYS_FSL_DDR_VER_47
1052 select SYS_FSL_ERRATUM_A004468
1053 select SYS_FSL_ERRATUM_A005871
1054 select SYS_FSL_ERRATUM_A006261
1055 select SYS_FSL_ERRATUM_A006379
1056 select SYS_FSL_ERRATUM_A006593
1057 select SYS_FSL_ERRATUM_A007186
1058 select SYS_FSL_ERRATUM_A007798
1059 select SYS_FSL_ERRATUM_A007815
1060 select SYS_FSL_ERRATUM_A007907
1061 select SYS_FSL_ERRATUM_A009942
1062 select SYS_FSL_HAS_DDR3
1063 select SYS_FSL_HAS_SEC
1064 select SYS_FSL_QORIQ_CHASSIS2
1065 select SYS_FSL_SEC_BE
1066 select SYS_FSL_SEC_COMPAT_4
1080 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1086 Enble PowerPC E500MC core
1091 Enable PowerPC E6500 core
1096 Use Freescale common code for Local Access Window
1101 Enable Freescale Secure Boot feature. Normally selected
1102 by defconfig. If unsure, do not change.
1105 int "Maximum number of CPUs permitted for MPC85xx"
1106 default 12 if ARCH_T4240
1107 default 8 if ARCH_P4080 || \
1109 default 4 if ARCH_B4860 || \
1117 default 2 if ARCH_B4420 || \
1132 Set this number to the maximum number of possible CPUs in the SoC.
1133 SoCs may have multiple clusters with each cluster may have multiple
1134 ports. If some ports are reserved but higher ports are used for
1135 cores, count the reserved ports. This will allocate enough memory
1136 in spin table to properly handle all cores.
1138 config SYS_CCSRBAR_DEFAULT
1139 hex "Default CCSRBAR address"
1140 default 0xff700000 if ARCH_BSC9131 || \
1161 default 0xff600000 if ARCH_P1023
1162 default 0xfe000000 if ARCH_B4420 || \
1177 default 0xe0000000 if ARCH_QEMU_E500
1179 Default value of CCSRBAR comes from power-on-reset. It
1180 is fixed on each SoC. Some SoCs can have different value
1181 if changed by pre-boot regime. The value here must match
1182 the current value in SoC. If not sure, do not change.
1184 config SYS_FSL_ERRATUM_A004468
1187 config SYS_FSL_ERRATUM_A004477
1190 config SYS_FSL_ERRATUM_A004508
1193 config SYS_FSL_ERRATUM_A004580
1196 config SYS_FSL_ERRATUM_A004699
1199 config SYS_FSL_ERRATUM_A004849
1202 config SYS_FSL_ERRATUM_A004510
1205 config SYS_FSL_ERRATUM_A004510_SVR_REV
1207 depends on SYS_FSL_ERRATUM_A004510
1208 default 0x20 if ARCH_P4080
1211 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1213 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1216 config SYS_FSL_ERRATUM_A005125
1219 config SYS_FSL_ERRATUM_A005434
1222 config SYS_FSL_ERRATUM_A005812
1225 config SYS_FSL_ERRATUM_A005871
1228 config SYS_FSL_ERRATUM_A006261
1231 config SYS_FSL_ERRATUM_A006379
1234 config SYS_FSL_ERRATUM_A006384
1237 config SYS_FSL_ERRATUM_A006475
1240 config SYS_FSL_ERRATUM_A006593
1243 config SYS_FSL_ERRATUM_A007075
1246 config SYS_FSL_ERRATUM_A007186
1249 config SYS_FSL_ERRATUM_A007212
1252 config SYS_FSL_ERRATUM_A007815
1255 config SYS_FSL_ERRATUM_A007798
1258 config SYS_FSL_ERRATUM_A007907
1261 config SYS_FSL_ERRATUM_A008044
1264 config SYS_FSL_ERRATUM_CPC_A002
1267 config SYS_FSL_ERRATUM_CPC_A003
1270 config SYS_FSL_ERRATUM_CPU_A003999
1273 config SYS_FSL_ERRATUM_ELBC_A001
1276 config SYS_FSL_ERRATUM_I2C_A004447
1279 config SYS_FSL_A004447_SVR_REV
1281 depends on SYS_FSL_ERRATUM_I2C_A004447
1282 default 0x00 if ARCH_MPC8548
1283 default 0x10 if ARCH_P1010
1284 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1285 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1287 config SYS_FSL_ERRATUM_IFC_A002769
1290 config SYS_FSL_ERRATUM_IFC_A003399
1293 config SYS_FSL_ERRATUM_NMG_CPU_A011
1296 config SYS_FSL_ERRATUM_NMG_ETSEC129
1299 config SYS_FSL_ERRATUM_NMG_LBC103
1302 config SYS_FSL_ERRATUM_P1010_A003549
1305 config SYS_FSL_ERRATUM_SATA_A001
1308 config SYS_FSL_ERRATUM_SEC_A003571
1311 config SYS_FSL_ERRATUM_SRIO_A004034
1314 config SYS_FSL_ERRATUM_USB14
1317 config SYS_P4080_ERRATUM_CPU22
1320 config SYS_P4080_ERRATUM_PCIE_A003
1323 config SYS_P4080_ERRATUM_SERDES8
1326 config SYS_P4080_ERRATUM_SERDES9
1329 config SYS_P4080_ERRATUM_SERDES_A001
1332 config SYS_P4080_ERRATUM_SERDES_A005
1335 config SYS_FSL_QORIQ_CHASSIS1
1338 config SYS_FSL_QORIQ_CHASSIS2
1341 config SYS_FSL_NUM_LAWS
1342 int "Number of local access windows"
1344 default 32 if ARCH_B4420 || \
1355 default 16 if ARCH_T1023 || \
1359 default 12 if ARCH_BSC9131 || \
1373 default 10 if ARCH_MPC8544 || \
1377 default 8 if ARCH_MPC8540 || \
1382 Number of local access windows. This is fixed per SoC.
1383 If not sure, do not change.
1385 config SYS_FSL_THREADS_PER_CORE
1390 config SYS_NUM_TLBCAMS
1391 int "Number of TLB CAM entries"
1392 default 64 if E500MC
1395 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1396 16 for other E500 SoCs.
1401 config SYS_PPC_E500_USE_DEBUG_TLB
1410 config SYS_PPC_E500_DEBUG_TLB
1411 int "Temporary TLB entry for external debugger"
1412 depends on SYS_PPC_E500_USE_DEBUG_TLB
1413 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1414 default 1 if ARCH_MPC8536
1415 default 2 if ARCH_MPC8572 || \
1423 default 3 if ARCH_P1010 || \
1427 Select a temporary TLB entry to be used during boot to work
1428 around limitations in e500v1 and e500v2 external debugger
1429 support. This reduces the portions of the boot code where
1430 breakpoints and single stepping do not work. The value of this
1431 symbol should be set to the TLB1 entry to be used for this
1432 purpose. If unsure, do not change.
1434 config SYS_FSL_IFC_CLK_DIV
1435 int "Divider of platform clock"
1437 default 2 if ARCH_B4420 || \
1447 Defines divider of platform clock(clock input to
1450 config SYS_FSL_LBC_CLK_DIV
1451 int "Divider of platform clock"
1452 depends on FSL_ELBC || ARCH_MPC8540 || \
1453 ARCH_MPC8548 || ARCH_MPC8541 || \
1454 ARCH_MPC8555 || ARCH_MPC8560 || \
1457 default 2 if ARCH_P2041 || \
1465 Defines divider of platform clock(clock input to
1468 source "board/freescale/b4860qds/Kconfig"
1469 source "board/freescale/bsc9131rdb/Kconfig"
1470 source "board/freescale/bsc9132qds/Kconfig"
1471 source "board/freescale/c29xpcie/Kconfig"
1472 source "board/freescale/corenet_ds/Kconfig"
1473 source "board/freescale/mpc8536ds/Kconfig"
1474 source "board/freescale/mpc8541cds/Kconfig"
1475 source "board/freescale/mpc8544ds/Kconfig"
1476 source "board/freescale/mpc8548cds/Kconfig"
1477 source "board/freescale/mpc8555cds/Kconfig"
1478 source "board/freescale/mpc8568mds/Kconfig"
1479 source "board/freescale/mpc8569mds/Kconfig"
1480 source "board/freescale/mpc8572ds/Kconfig"
1481 source "board/freescale/p1010rdb/Kconfig"
1482 source "board/freescale/p1022ds/Kconfig"
1483 source "board/freescale/p1023rdb/Kconfig"
1484 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1485 source "board/freescale/p1_twr/Kconfig"
1486 source "board/freescale/p2041rdb/Kconfig"
1487 source "board/freescale/qemu-ppce500/Kconfig"
1488 source "board/freescale/t102xqds/Kconfig"
1489 source "board/freescale/t102xrdb/Kconfig"
1490 source "board/freescale/t1040qds/Kconfig"
1491 source "board/freescale/t104xrdb/Kconfig"
1492 source "board/freescale/t208xqds/Kconfig"
1493 source "board/freescale/t208xrdb/Kconfig"
1494 source "board/freescale/t4qds/Kconfig"
1495 source "board/freescale/t4rdb/Kconfig"
1496 source "board/gdsys/p1022/Kconfig"
1497 source "board/keymile/kmp204x/Kconfig"
1498 source "board/sbc8548/Kconfig"
1499 source "board/socrates/Kconfig"
1500 source "board/varisys/cyrus/Kconfig"
1501 source "board/xes/xpedite520x/Kconfig"
1502 source "board/xes/xpedite537x/Kconfig"
1503 source "board/xes/xpedite550x/Kconfig"
1504 source "board/Arcturus/ucp1020/Kconfig"