8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
24 config TARGET_SOCRATES
25 bool "Support socrates"
28 config TARGET_B4420QDS
29 bool "Support B4420QDS"
34 config TARGET_B4860QDS
35 bool "Support B4860QDS"
37 select BOARD_LATE_INIT if CHAIN_OF_TRUST
41 config TARGET_BSC9131RDB
42 bool "Support BSC9131RDB"
45 select BOARD_EARLY_INIT_F
47 config TARGET_BSC9132QDS
48 bool "Support BSC9132QDS"
50 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 select BOARD_EARLY_INIT_F
54 config TARGET_C29XPCIE
55 bool "Support C29XPCIE"
57 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 bool "Support P3041DS"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
70 bool "Support P4080DS"
73 select BOARD_LATE_INIT if CHAIN_OF_TRUST
77 bool "Support P5020DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
84 bool "Support P5040DS"
87 select BOARD_LATE_INIT if CHAIN_OF_TRUST
90 config TARGET_MPC8536DS
91 bool "Support MPC8536DS"
93 # Use DDR3 controller with DDR2 DIMMs on this board
94 select SYS_FSL_DDRC_GEN3
97 config TARGET_MPC8541CDS
98 bool "Support MPC8541CDS"
101 config TARGET_MPC8544DS
102 bool "Support MPC8544DS"
105 config TARGET_MPC8548CDS
106 bool "Support MPC8548CDS"
108 imply ENV_IS_IN_FLASH
110 config TARGET_MPC8555CDS
111 bool "Support MPC8555CDS"
114 config TARGET_MPC8568MDS
115 bool "Support MPC8568MDS"
118 config TARGET_MPC8569MDS
119 bool "Support MPC8569MDS"
122 config TARGET_MPC8572DS
123 bool "Support MPC8572DS"
125 # Use DDR3 controller with DDR2 DIMMs on this board
126 select SYS_FSL_DDRC_GEN3
129 config TARGET_P1010RDB_PA
130 bool "Support P1010RDB_PA"
132 select BOARD_LATE_INIT if CHAIN_OF_TRUST
138 config TARGET_P1010RDB_PB
139 bool "Support P1010RDB_PB"
141 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_P1022DS
148 bool "Support P1022DS"
154 config TARGET_P1023RDB
155 bool "Support P1023RDB"
159 config TARGET_P1020MBG
160 bool "Support P1020MBG-PC"
167 config TARGET_P1020RDB_PC
168 bool "Support P1020RDB-PC"
175 config TARGET_P1020RDB_PD
176 bool "Support P1020RDB-PD"
183 config TARGET_P1020UTM
184 bool "Support P1020UTM"
191 config TARGET_P1021RDB
192 bool "Support P1021RDB"
199 config TARGET_P1024RDB
200 bool "Support P1024RDB"
207 config TARGET_P1025RDB
208 bool "Support P1025RDB"
215 config TARGET_P2020RDB
216 bool "Support P2020RDB-PC"
224 bool "Support p1_twr"
227 config TARGET_P2041RDB
228 bool "Support P2041RDB"
230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
234 config TARGET_QEMU_PPCE500
235 bool "Support qemu-ppce500"
236 select ARCH_QEMU_E500
239 config TARGET_T1024QDS
240 bool "Support T1024QDS"
242 select BOARD_LATE_INIT if CHAIN_OF_TRUST
248 config TARGET_T1023RDB
249 bool "Support T1023RDB"
251 select BOARD_LATE_INIT if CHAIN_OF_TRUST
256 config TARGET_T1024RDB
257 bool "Support T1024RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
264 config TARGET_T1040QDS
265 bool "Support T1040QDS"
267 select BOARD_LATE_INIT if CHAIN_OF_TRUST
272 config TARGET_T1040RDB
273 bool "Support T1040RDB"
275 select BOARD_LATE_INIT if CHAIN_OF_TRUST
280 config TARGET_T1040D4RDB
281 bool "Support T1040D4RDB"
283 select BOARD_LATE_INIT if CHAIN_OF_TRUST
288 config TARGET_T1042RDB
289 bool "Support T1042RDB"
291 select BOARD_LATE_INIT if CHAIN_OF_TRUST
296 config TARGET_T1042D4RDB
297 bool "Support T1042D4RDB"
299 select BOARD_LATE_INIT if CHAIN_OF_TRUST
304 config TARGET_T1042RDB_PI
305 bool "Support T1042RDB_PI"
307 select BOARD_LATE_INIT if CHAIN_OF_TRUST
312 config TARGET_T2080QDS
313 bool "Support T2080QDS"
315 select BOARD_LATE_INIT if CHAIN_OF_TRUST
320 config TARGET_T2080RDB
321 bool "Support T2080RDB"
323 select BOARD_LATE_INIT if CHAIN_OF_TRUST
328 config TARGET_T2081QDS
329 bool "Support T2081QDS"
334 config TARGET_T4160QDS
335 bool "Support T4160QDS"
337 select BOARD_LATE_INIT if CHAIN_OF_TRUST
342 config TARGET_T4160RDB
343 bool "Support T4160RDB"
348 config TARGET_T4240QDS
349 bool "Support T4240QDS"
351 select BOARD_LATE_INIT if CHAIN_OF_TRUST
356 config TARGET_T4240RDB
357 bool "Support T4240RDB"
363 config TARGET_CONTROLCENTERD
364 bool "Support controlcenterd"
367 config TARGET_KMP204X
368 bool "Support kmp204x"
374 config TARGET_XPEDITE520X
375 bool "Support xpedite520x"
378 config TARGET_XPEDITE537X
379 bool "Support xpedite537x"
381 # Use DDR3 controller with DDR2 DIMMs on this board
382 select SYS_FSL_DDRC_GEN3
384 config TARGET_XPEDITE550X
385 bool "Support xpedite550x"
388 config TARGET_UCP1020
389 bool "Support uCP1020"
393 config TARGET_CYRUS_P5020
394 bool "Support Varisys Cyrus P5020"
398 config TARGET_CYRUS_P5040
399 bool "Support Varisys Cyrus P5040"
410 select SYS_FSL_DDR_VER_47
411 select SYS_FSL_ERRATUM_A004477
412 select SYS_FSL_ERRATUM_A005871
413 select SYS_FSL_ERRATUM_A006379
414 select SYS_FSL_ERRATUM_A006384
415 select SYS_FSL_ERRATUM_A006475
416 select SYS_FSL_ERRATUM_A006593
417 select SYS_FSL_ERRATUM_A007075
418 select SYS_FSL_ERRATUM_A007186
419 select SYS_FSL_ERRATUM_A007212
420 select SYS_FSL_ERRATUM_A009942
421 select SYS_FSL_HAS_DDR3
422 select SYS_FSL_HAS_SEC
423 select SYS_FSL_QORIQ_CHASSIS2
424 select SYS_FSL_SEC_BE
425 select SYS_FSL_SEC_COMPAT_4
437 select SYS_FSL_DDR_VER_47
438 select SYS_FSL_ERRATUM_A004477
439 select SYS_FSL_ERRATUM_A005871
440 select SYS_FSL_ERRATUM_A006379
441 select SYS_FSL_ERRATUM_A006384
442 select SYS_FSL_ERRATUM_A006475
443 select SYS_FSL_ERRATUM_A006593
444 select SYS_FSL_ERRATUM_A007075
445 select SYS_FSL_ERRATUM_A007186
446 select SYS_FSL_ERRATUM_A007212
447 select SYS_FSL_ERRATUM_A007907
448 select SYS_FSL_ERRATUM_A009942
449 select SYS_FSL_HAS_DDR3
450 select SYS_FSL_HAS_SEC
451 select SYS_FSL_QORIQ_CHASSIS2
452 select SYS_FSL_SEC_BE
453 select SYS_FSL_SEC_COMPAT_4
463 select SYS_FSL_DDR_VER_44
464 select SYS_FSL_ERRATUM_A004477
465 select SYS_FSL_ERRATUM_A005125
466 select SYS_FSL_ERRATUM_ESDHC111
467 select SYS_FSL_HAS_DDR3
468 select SYS_FSL_HAS_SEC
469 select SYS_FSL_SEC_BE
470 select SYS_FSL_SEC_COMPAT_4
479 select SYS_FSL_DDR_VER_46
480 select SYS_FSL_ERRATUM_A004477
481 select SYS_FSL_ERRATUM_A005125
482 select SYS_FSL_ERRATUM_A005434
483 select SYS_FSL_ERRATUM_ESDHC111
484 select SYS_FSL_ERRATUM_I2C_A004447
485 select SYS_FSL_ERRATUM_IFC_A002769
486 select SYS_FSL_HAS_DDR3
487 select SYS_FSL_HAS_SEC
488 select SYS_FSL_SEC_BE
489 select SYS_FSL_SEC_COMPAT_4
490 select SYS_PPC_E500_USE_DEBUG_TLB
501 select SYS_FSL_DDR_VER_46
502 select SYS_FSL_ERRATUM_A005125
503 select SYS_FSL_ERRATUM_ESDHC111
504 select SYS_FSL_HAS_DDR3
505 select SYS_FSL_HAS_SEC
506 select SYS_FSL_SEC_BE
507 select SYS_FSL_SEC_COMPAT_6
508 select SYS_PPC_E500_USE_DEBUG_TLB
517 select SYS_FSL_ERRATUM_A004508
518 select SYS_FSL_ERRATUM_A005125
519 select SYS_FSL_HAS_DDR2
520 select SYS_FSL_HAS_DDR3
521 select SYS_FSL_HAS_SEC
522 select SYS_FSL_SEC_BE
523 select SYS_FSL_SEC_COMPAT_2
524 select SYS_PPC_E500_USE_DEBUG_TLB
533 select SYS_FSL_HAS_DDR1
538 select SYS_FSL_HAS_DDR1
539 select SYS_FSL_HAS_SEC
540 select SYS_FSL_SEC_BE
541 select SYS_FSL_SEC_COMPAT_2
546 select SYS_FSL_ERRATUM_A005125
547 select SYS_FSL_HAS_DDR2
548 select SYS_FSL_HAS_SEC
549 select SYS_FSL_SEC_BE
550 select SYS_FSL_SEC_COMPAT_2
551 select SYS_PPC_E500_USE_DEBUG_TLB
557 select SYS_FSL_ERRATUM_A005125
558 select SYS_FSL_ERRATUM_NMG_DDR120
559 select SYS_FSL_ERRATUM_NMG_LBC103
560 select SYS_FSL_ERRATUM_NMG_ETSEC129
561 select SYS_FSL_ERRATUM_I2C_A004447
562 select SYS_FSL_HAS_DDR2
563 select SYS_FSL_HAS_DDR1
564 select SYS_FSL_HAS_SEC
565 select SYS_FSL_SEC_BE
566 select SYS_FSL_SEC_COMPAT_2
567 select SYS_PPC_E500_USE_DEBUG_TLB
568 imply ENV_IS_IN_FLASH
574 select SYS_FSL_HAS_DDR1
575 select SYS_FSL_HAS_SEC
576 select SYS_FSL_SEC_BE
577 select SYS_FSL_SEC_COMPAT_2
582 select SYS_FSL_HAS_DDR1
587 select SYS_FSL_HAS_DDR2
588 select SYS_FSL_HAS_SEC
589 select SYS_FSL_SEC_BE
590 select SYS_FSL_SEC_COMPAT_2
595 select SYS_FSL_ERRATUM_A004508
596 select SYS_FSL_ERRATUM_A005125
597 select SYS_FSL_HAS_DDR3
598 select SYS_FSL_HAS_SEC
599 select SYS_FSL_SEC_BE
600 select SYS_FSL_SEC_COMPAT_2
607 select SYS_FSL_ERRATUM_A004508
608 select SYS_FSL_ERRATUM_A005125
609 select SYS_FSL_ERRATUM_DDR_115
610 select SYS_FSL_ERRATUM_DDR111_DDR134
611 select SYS_FSL_HAS_DDR2
612 select SYS_FSL_HAS_DDR3
613 select SYS_FSL_HAS_SEC
614 select SYS_FSL_SEC_BE
615 select SYS_FSL_SEC_COMPAT_2
616 select SYS_PPC_E500_USE_DEBUG_TLB
619 imply ENV_IS_IN_FLASH
624 select SYS_FSL_ERRATUM_A004477
625 select SYS_FSL_ERRATUM_A004508
626 select SYS_FSL_ERRATUM_A005125
627 select SYS_FSL_ERRATUM_A006261
628 select SYS_FSL_ERRATUM_A007075
629 select SYS_FSL_ERRATUM_ESDHC111
630 select SYS_FSL_ERRATUM_I2C_A004447
631 select SYS_FSL_ERRATUM_IFC_A002769
632 select SYS_FSL_ERRATUM_P1010_A003549
633 select SYS_FSL_ERRATUM_SEC_A003571
634 select SYS_FSL_ERRATUM_IFC_A003399
635 select SYS_FSL_HAS_DDR3
636 select SYS_FSL_HAS_SEC
637 select SYS_FSL_SEC_BE
638 select SYS_FSL_SEC_COMPAT_4
639 select SYS_PPC_E500_USE_DEBUG_TLB
651 select SYS_FSL_ERRATUM_A004508
652 select SYS_FSL_ERRATUM_A005125
653 select SYS_FSL_ERRATUM_ELBC_A001
654 select SYS_FSL_ERRATUM_ESDHC111
655 select SYS_FSL_HAS_DDR3
656 select SYS_FSL_HAS_SEC
657 select SYS_FSL_SEC_BE
658 select SYS_FSL_SEC_COMPAT_2
659 select SYS_PPC_E500_USE_DEBUG_TLB
665 select SYS_FSL_ERRATUM_A004508
666 select SYS_FSL_ERRATUM_A005125
667 select SYS_FSL_ERRATUM_ELBC_A001
668 select SYS_FSL_ERRATUM_ESDHC111
669 select SYS_FSL_HAS_DDR3
670 select SYS_FSL_HAS_SEC
671 select SYS_FSL_SEC_BE
672 select SYS_FSL_SEC_COMPAT_2
673 select SYS_PPC_E500_USE_DEBUG_TLB
683 select SYS_FSL_ERRATUM_A004508
684 select SYS_FSL_ERRATUM_A005125
685 select SYS_FSL_ERRATUM_ELBC_A001
686 select SYS_FSL_ERRATUM_ESDHC111
687 select SYS_FSL_HAS_DDR3
688 select SYS_FSL_HAS_SEC
689 select SYS_FSL_SEC_BE
690 select SYS_FSL_SEC_COMPAT_2
691 select SYS_PPC_E500_USE_DEBUG_TLB
701 select SYS_FSL_ERRATUM_A004477
702 select SYS_FSL_ERRATUM_A004508
703 select SYS_FSL_ERRATUM_A005125
704 select SYS_FSL_ERRATUM_ELBC_A001
705 select SYS_FSL_ERRATUM_ESDHC111
706 select SYS_FSL_ERRATUM_SATA_A001
707 select SYS_FSL_HAS_DDR3
708 select SYS_FSL_HAS_SEC
709 select SYS_FSL_SEC_BE
710 select SYS_FSL_SEC_COMPAT_2
711 select SYS_PPC_E500_USE_DEBUG_TLB
717 select SYS_FSL_ERRATUM_A004508
718 select SYS_FSL_ERRATUM_A005125
719 select SYS_FSL_ERRATUM_I2C_A004447
720 select SYS_FSL_HAS_DDR3
721 select SYS_FSL_HAS_SEC
722 select SYS_FSL_SEC_BE
723 select SYS_FSL_SEC_COMPAT_4
729 select SYS_FSL_ERRATUM_A004508
730 select SYS_FSL_ERRATUM_A005125
731 select SYS_FSL_ERRATUM_ELBC_A001
732 select SYS_FSL_ERRATUM_ESDHC111
733 select SYS_FSL_HAS_DDR3
734 select SYS_FSL_HAS_SEC
735 select SYS_FSL_SEC_BE
736 select SYS_FSL_SEC_COMPAT_2
737 select SYS_PPC_E500_USE_DEBUG_TLB
748 select SYS_FSL_ERRATUM_A004508
749 select SYS_FSL_ERRATUM_A005125
750 select SYS_FSL_ERRATUM_ELBC_A001
751 select SYS_FSL_ERRATUM_ESDHC111
752 select SYS_FSL_HAS_DDR3
753 select SYS_FSL_HAS_SEC
754 select SYS_FSL_SEC_BE
755 select SYS_FSL_SEC_COMPAT_2
756 select SYS_PPC_E500_USE_DEBUG_TLB
764 select SYS_FSL_ERRATUM_A004477
765 select SYS_FSL_ERRATUM_A004508
766 select SYS_FSL_ERRATUM_A005125
767 select SYS_FSL_ERRATUM_ESDHC111
768 select SYS_FSL_ERRATUM_ESDHC_A001
769 select SYS_FSL_HAS_DDR3
770 select SYS_FSL_HAS_SEC
771 select SYS_FSL_SEC_BE
772 select SYS_FSL_SEC_COMPAT_2
773 select SYS_PPC_E500_USE_DEBUG_TLB
783 select SYS_FSL_ERRATUM_A004510
784 select SYS_FSL_ERRATUM_A004849
785 select SYS_FSL_ERRATUM_A006261
786 select SYS_FSL_ERRATUM_CPU_A003999
787 select SYS_FSL_ERRATUM_DDR_A003
788 select SYS_FSL_ERRATUM_DDR_A003474
789 select SYS_FSL_ERRATUM_ESDHC111
790 select SYS_FSL_ERRATUM_I2C_A004447
791 select SYS_FSL_ERRATUM_NMG_CPU_A011
792 select SYS_FSL_ERRATUM_SRIO_A004034
793 select SYS_FSL_ERRATUM_USB14
794 select SYS_FSL_HAS_DDR3
795 select SYS_FSL_HAS_SEC
796 select SYS_FSL_QORIQ_CHASSIS1
797 select SYS_FSL_SEC_BE
798 select SYS_FSL_SEC_COMPAT_4
806 select SYS_FSL_DDR_VER_44
807 select SYS_FSL_ERRATUM_A004510
808 select SYS_FSL_ERRATUM_A004849
809 select SYS_FSL_ERRATUM_A005812
810 select SYS_FSL_ERRATUM_A006261
811 select SYS_FSL_ERRATUM_CPU_A003999
812 select SYS_FSL_ERRATUM_DDR_A003
813 select SYS_FSL_ERRATUM_DDR_A003474
814 select SYS_FSL_ERRATUM_ESDHC111
815 select SYS_FSL_ERRATUM_I2C_A004447
816 select SYS_FSL_ERRATUM_NMG_CPU_A011
817 select SYS_FSL_ERRATUM_SRIO_A004034
818 select SYS_FSL_ERRATUM_USB14
819 select SYS_FSL_HAS_DDR3
820 select SYS_FSL_HAS_SEC
821 select SYS_FSL_QORIQ_CHASSIS1
822 select SYS_FSL_SEC_BE
823 select SYS_FSL_SEC_COMPAT_4
833 select SYS_FSL_DDR_VER_44
834 select SYS_FSL_ERRATUM_A004510
835 select SYS_FSL_ERRATUM_A004580
836 select SYS_FSL_ERRATUM_A004849
837 select SYS_FSL_ERRATUM_A005812
838 select SYS_FSL_ERRATUM_A007075
839 select SYS_FSL_ERRATUM_CPC_A002
840 select SYS_FSL_ERRATUM_CPC_A003
841 select SYS_FSL_ERRATUM_CPU_A003999
842 select SYS_FSL_ERRATUM_DDR_A003
843 select SYS_FSL_ERRATUM_DDR_A003474
844 select SYS_FSL_ERRATUM_ELBC_A001
845 select SYS_FSL_ERRATUM_ESDHC111
846 select SYS_FSL_ERRATUM_ESDHC13
847 select SYS_FSL_ERRATUM_ESDHC135
848 select SYS_FSL_ERRATUM_I2C_A004447
849 select SYS_FSL_ERRATUM_NMG_CPU_A011
850 select SYS_FSL_ERRATUM_SRIO_A004034
851 select SYS_P4080_ERRATUM_CPU22
852 select SYS_P4080_ERRATUM_PCIE_A003
853 select SYS_P4080_ERRATUM_SERDES8
854 select SYS_P4080_ERRATUM_SERDES9
855 select SYS_P4080_ERRATUM_SERDES_A001
856 select SYS_P4080_ERRATUM_SERDES_A005
857 select SYS_FSL_HAS_DDR3
858 select SYS_FSL_HAS_SEC
859 select SYS_FSL_QORIQ_CHASSIS1
860 select SYS_FSL_SEC_BE
861 select SYS_FSL_SEC_COMPAT_4
870 select SYS_FSL_DDR_VER_44
871 select SYS_FSL_ERRATUM_A004510
872 select SYS_FSL_ERRATUM_A006261
873 select SYS_FSL_ERRATUM_DDR_A003
874 select SYS_FSL_ERRATUM_DDR_A003474
875 select SYS_FSL_ERRATUM_ESDHC111
876 select SYS_FSL_ERRATUM_I2C_A004447
877 select SYS_FSL_ERRATUM_SRIO_A004034
878 select SYS_FSL_ERRATUM_USB14
879 select SYS_FSL_HAS_DDR3
880 select SYS_FSL_HAS_SEC
881 select SYS_FSL_QORIQ_CHASSIS1
882 select SYS_FSL_SEC_BE
883 select SYS_FSL_SEC_COMPAT_4
893 select SYS_FSL_DDR_VER_44
894 select SYS_FSL_ERRATUM_A004510
895 select SYS_FSL_ERRATUM_A004699
896 select SYS_FSL_ERRATUM_A005812
897 select SYS_FSL_ERRATUM_A006261
898 select SYS_FSL_ERRATUM_DDR_A003
899 select SYS_FSL_ERRATUM_DDR_A003474
900 select SYS_FSL_ERRATUM_ESDHC111
901 select SYS_FSL_ERRATUM_USB14
902 select SYS_FSL_HAS_DDR3
903 select SYS_FSL_HAS_SEC
904 select SYS_FSL_QORIQ_CHASSIS1
905 select SYS_FSL_SEC_BE
906 select SYS_FSL_SEC_COMPAT_4
912 config ARCH_QEMU_E500
919 select SYS_FSL_DDR_VER_50
920 select SYS_FSL_ERRATUM_A008378
921 select SYS_FSL_ERRATUM_A009663
922 select SYS_FSL_ERRATUM_A009942
923 select SYS_FSL_ERRATUM_ESDHC111
924 select SYS_FSL_HAS_DDR3
925 select SYS_FSL_HAS_DDR4
926 select SYS_FSL_HAS_SEC
927 select SYS_FSL_QORIQ_CHASSIS2
928 select SYS_FSL_SEC_BE
929 select SYS_FSL_SEC_COMPAT_5
939 select SYS_FSL_DDR_VER_50
940 select SYS_FSL_ERRATUM_A008378
941 select SYS_FSL_ERRATUM_A009663
942 select SYS_FSL_ERRATUM_A009942
943 select SYS_FSL_ERRATUM_ESDHC111
944 select SYS_FSL_HAS_DDR3
945 select SYS_FSL_HAS_DDR4
946 select SYS_FSL_HAS_SEC
947 select SYS_FSL_QORIQ_CHASSIS2
948 select SYS_FSL_SEC_BE
949 select SYS_FSL_SEC_COMPAT_5
960 select SYS_FSL_DDR_VER_50
961 select SYS_FSL_ERRATUM_A008044
962 select SYS_FSL_ERRATUM_A008378
963 select SYS_FSL_ERRATUM_A009663
964 select SYS_FSL_ERRATUM_A009942
965 select SYS_FSL_ERRATUM_ESDHC111
966 select SYS_FSL_HAS_DDR3
967 select SYS_FSL_HAS_DDR4
968 select SYS_FSL_HAS_SEC
969 select SYS_FSL_QORIQ_CHASSIS2
970 select SYS_FSL_SEC_BE
971 select SYS_FSL_SEC_COMPAT_5
982 select SYS_FSL_DDR_VER_50
983 select SYS_FSL_ERRATUM_A008044
984 select SYS_FSL_ERRATUM_A008378
985 select SYS_FSL_ERRATUM_A009663
986 select SYS_FSL_ERRATUM_A009942
987 select SYS_FSL_ERRATUM_ESDHC111
988 select SYS_FSL_HAS_DDR3
989 select SYS_FSL_HAS_DDR4
990 select SYS_FSL_HAS_SEC
991 select SYS_FSL_QORIQ_CHASSIS2
992 select SYS_FSL_SEC_BE
993 select SYS_FSL_SEC_COMPAT_5
1005 select SYS_FSL_DDR_VER_47
1006 select SYS_FSL_ERRATUM_A006379
1007 select SYS_FSL_ERRATUM_A006593
1008 select SYS_FSL_ERRATUM_A007186
1009 select SYS_FSL_ERRATUM_A007212
1010 select SYS_FSL_ERRATUM_A007815
1011 select SYS_FSL_ERRATUM_A007907
1012 select SYS_FSL_ERRATUM_A009942
1013 select SYS_FSL_ERRATUM_ESDHC111
1014 select SYS_FSL_HAS_DDR3
1015 select SYS_FSL_HAS_SEC
1016 select SYS_FSL_QORIQ_CHASSIS2
1017 select SYS_FSL_SEC_BE
1018 select SYS_FSL_SEC_COMPAT_4
1030 select SYS_FSL_DDR_VER_47
1031 select SYS_FSL_ERRATUM_A006379
1032 select SYS_FSL_ERRATUM_A006593
1033 select SYS_FSL_ERRATUM_A007186
1034 select SYS_FSL_ERRATUM_A007212
1035 select SYS_FSL_ERRATUM_A009942
1036 select SYS_FSL_ERRATUM_ESDHC111
1037 select SYS_FSL_HAS_DDR3
1038 select SYS_FSL_HAS_SEC
1039 select SYS_FSL_QORIQ_CHASSIS2
1040 select SYS_FSL_SEC_BE
1041 select SYS_FSL_SEC_COMPAT_4
1052 select SYS_FSL_DDR_VER_47
1053 select SYS_FSL_ERRATUM_A004468
1054 select SYS_FSL_ERRATUM_A005871
1055 select SYS_FSL_ERRATUM_A006379
1056 select SYS_FSL_ERRATUM_A006593
1057 select SYS_FSL_ERRATUM_A007186
1058 select SYS_FSL_ERRATUM_A007798
1059 select SYS_FSL_ERRATUM_A009942
1060 select SYS_FSL_HAS_DDR3
1061 select SYS_FSL_HAS_SEC
1062 select SYS_FSL_QORIQ_CHASSIS2
1063 select SYS_FSL_SEC_BE
1064 select SYS_FSL_SEC_COMPAT_4
1076 select SYS_FSL_DDR_VER_47
1077 select SYS_FSL_ERRATUM_A004468
1078 select SYS_FSL_ERRATUM_A005871
1079 select SYS_FSL_ERRATUM_A006261
1080 select SYS_FSL_ERRATUM_A006379
1081 select SYS_FSL_ERRATUM_A006593
1082 select SYS_FSL_ERRATUM_A007186
1083 select SYS_FSL_ERRATUM_A007798
1084 select SYS_FSL_ERRATUM_A007815
1085 select SYS_FSL_ERRATUM_A007907
1086 select SYS_FSL_ERRATUM_A009942
1087 select SYS_FSL_HAS_DDR3
1088 select SYS_FSL_HAS_SEC
1089 select SYS_FSL_QORIQ_CHASSIS2
1090 select SYS_FSL_SEC_BE
1091 select SYS_FSL_SEC_COMPAT_4
1106 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1112 Enble PowerPC E500MC core
1117 Enable PowerPC E6500 core
1122 Use Freescale common code for Local Access Window
1127 Enable Freescale Secure Boot feature. Normally selected
1128 by defconfig. If unsure, do not change.
1131 int "Maximum number of CPUs permitted for MPC85xx"
1132 default 12 if ARCH_T4240
1133 default 8 if ARCH_P4080 || \
1135 default 4 if ARCH_B4860 || \
1143 default 2 if ARCH_B4420 || \
1158 Set this number to the maximum number of possible CPUs in the SoC.
1159 SoCs may have multiple clusters with each cluster may have multiple
1160 ports. If some ports are reserved but higher ports are used for
1161 cores, count the reserved ports. This will allocate enough memory
1162 in spin table to properly handle all cores.
1164 config SYS_CCSRBAR_DEFAULT
1165 hex "Default CCSRBAR address"
1166 default 0xff700000 if ARCH_BSC9131 || \
1187 default 0xff600000 if ARCH_P1023
1188 default 0xfe000000 if ARCH_B4420 || \
1203 default 0xe0000000 if ARCH_QEMU_E500
1205 Default value of CCSRBAR comes from power-on-reset. It
1206 is fixed on each SoC. Some SoCs can have different value
1207 if changed by pre-boot regime. The value here must match
1208 the current value in SoC. If not sure, do not change.
1210 config SYS_FSL_ERRATUM_A004468
1213 config SYS_FSL_ERRATUM_A004477
1216 config SYS_FSL_ERRATUM_A004508
1219 config SYS_FSL_ERRATUM_A004580
1222 config SYS_FSL_ERRATUM_A004699
1225 config SYS_FSL_ERRATUM_A004849
1228 config SYS_FSL_ERRATUM_A004510
1231 config SYS_FSL_ERRATUM_A004510_SVR_REV
1233 depends on SYS_FSL_ERRATUM_A004510
1234 default 0x20 if ARCH_P4080
1237 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1239 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1242 config SYS_FSL_ERRATUM_A005125
1245 config SYS_FSL_ERRATUM_A005434
1248 config SYS_FSL_ERRATUM_A005812
1251 config SYS_FSL_ERRATUM_A005871
1254 config SYS_FSL_ERRATUM_A006261
1257 config SYS_FSL_ERRATUM_A006379
1260 config SYS_FSL_ERRATUM_A006384
1263 config SYS_FSL_ERRATUM_A006475
1266 config SYS_FSL_ERRATUM_A006593
1269 config SYS_FSL_ERRATUM_A007075
1272 config SYS_FSL_ERRATUM_A007186
1275 config SYS_FSL_ERRATUM_A007212
1278 config SYS_FSL_ERRATUM_A007815
1281 config SYS_FSL_ERRATUM_A007798
1284 config SYS_FSL_ERRATUM_A007907
1287 config SYS_FSL_ERRATUM_A008044
1290 config SYS_FSL_ERRATUM_CPC_A002
1293 config SYS_FSL_ERRATUM_CPC_A003
1296 config SYS_FSL_ERRATUM_CPU_A003999
1299 config SYS_FSL_ERRATUM_ELBC_A001
1302 config SYS_FSL_ERRATUM_I2C_A004447
1305 config SYS_FSL_A004447_SVR_REV
1307 depends on SYS_FSL_ERRATUM_I2C_A004447
1308 default 0x00 if ARCH_MPC8548
1309 default 0x10 if ARCH_P1010
1310 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1311 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1313 config SYS_FSL_ERRATUM_IFC_A002769
1316 config SYS_FSL_ERRATUM_IFC_A003399
1319 config SYS_FSL_ERRATUM_NMG_CPU_A011
1322 config SYS_FSL_ERRATUM_NMG_ETSEC129
1325 config SYS_FSL_ERRATUM_NMG_LBC103
1328 config SYS_FSL_ERRATUM_P1010_A003549
1331 config SYS_FSL_ERRATUM_SATA_A001
1334 config SYS_FSL_ERRATUM_SEC_A003571
1337 config SYS_FSL_ERRATUM_SRIO_A004034
1340 config SYS_FSL_ERRATUM_USB14
1343 config SYS_P4080_ERRATUM_CPU22
1346 config SYS_P4080_ERRATUM_PCIE_A003
1349 config SYS_P4080_ERRATUM_SERDES8
1352 config SYS_P4080_ERRATUM_SERDES9
1355 config SYS_P4080_ERRATUM_SERDES_A001
1358 config SYS_P4080_ERRATUM_SERDES_A005
1361 config SYS_FSL_QORIQ_CHASSIS1
1364 config SYS_FSL_QORIQ_CHASSIS2
1367 config SYS_FSL_NUM_LAWS
1368 int "Number of local access windows"
1370 default 32 if ARCH_B4420 || \
1381 default 16 if ARCH_T1023 || \
1385 default 12 if ARCH_BSC9131 || \
1399 default 10 if ARCH_MPC8544 || \
1403 default 8 if ARCH_MPC8540 || \
1408 Number of local access windows. This is fixed per SoC.
1409 If not sure, do not change.
1411 config SYS_FSL_THREADS_PER_CORE
1416 config SYS_NUM_TLBCAMS
1417 int "Number of TLB CAM entries"
1418 default 64 if E500MC
1421 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1422 16 for other E500 SoCs.
1427 config SYS_PPC_E500_USE_DEBUG_TLB
1436 config SYS_PPC_E500_DEBUG_TLB
1437 int "Temporary TLB entry for external debugger"
1438 depends on SYS_PPC_E500_USE_DEBUG_TLB
1439 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1440 default 1 if ARCH_MPC8536
1441 default 2 if ARCH_MPC8572 || \
1449 default 3 if ARCH_P1010 || \
1453 Select a temporary TLB entry to be used during boot to work
1454 around limitations in e500v1 and e500v2 external debugger
1455 support. This reduces the portions of the boot code where
1456 breakpoints and single stepping do not work. The value of this
1457 symbol should be set to the TLB1 entry to be used for this
1458 purpose. If unsure, do not change.
1460 config SYS_FSL_IFC_CLK_DIV
1461 int "Divider of platform clock"
1463 default 2 if ARCH_B4420 || \
1473 Defines divider of platform clock(clock input to
1476 config SYS_FSL_LBC_CLK_DIV
1477 int "Divider of platform clock"
1478 depends on FSL_ELBC || ARCH_MPC8540 || \
1479 ARCH_MPC8548 || ARCH_MPC8541 || \
1480 ARCH_MPC8555 || ARCH_MPC8560 || \
1483 default 2 if ARCH_P2041 || \
1491 Defines divider of platform clock(clock input to
1494 source "board/freescale/b4860qds/Kconfig"
1495 source "board/freescale/bsc9131rdb/Kconfig"
1496 source "board/freescale/bsc9132qds/Kconfig"
1497 source "board/freescale/c29xpcie/Kconfig"
1498 source "board/freescale/corenet_ds/Kconfig"
1499 source "board/freescale/mpc8536ds/Kconfig"
1500 source "board/freescale/mpc8541cds/Kconfig"
1501 source "board/freescale/mpc8544ds/Kconfig"
1502 source "board/freescale/mpc8548cds/Kconfig"
1503 source "board/freescale/mpc8555cds/Kconfig"
1504 source "board/freescale/mpc8568mds/Kconfig"
1505 source "board/freescale/mpc8569mds/Kconfig"
1506 source "board/freescale/mpc8572ds/Kconfig"
1507 source "board/freescale/p1010rdb/Kconfig"
1508 source "board/freescale/p1022ds/Kconfig"
1509 source "board/freescale/p1023rdb/Kconfig"
1510 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1511 source "board/freescale/p1_twr/Kconfig"
1512 source "board/freescale/p2041rdb/Kconfig"
1513 source "board/freescale/qemu-ppce500/Kconfig"
1514 source "board/freescale/t102xqds/Kconfig"
1515 source "board/freescale/t102xrdb/Kconfig"
1516 source "board/freescale/t1040qds/Kconfig"
1517 source "board/freescale/t104xrdb/Kconfig"
1518 source "board/freescale/t208xqds/Kconfig"
1519 source "board/freescale/t208xrdb/Kconfig"
1520 source "board/freescale/t4qds/Kconfig"
1521 source "board/freescale/t4rdb/Kconfig"
1522 source "board/gdsys/p1022/Kconfig"
1523 source "board/keymile/kmp204x/Kconfig"
1524 source "board/sbc8548/Kconfig"
1525 source "board/socrates/Kconfig"
1526 source "board/varisys/cyrus/Kconfig"
1527 source "board/xes/xpedite520x/Kconfig"
1528 source "board/xes/xpedite537x/Kconfig"
1529 source "board/xes/xpedite550x/Kconfig"
1530 source "board/Arcturus/ucp1020/Kconfig"