12 bool "Support sbc8548"
15 config TARGET_SOCRATES
16 bool "Support socrates"
19 config TARGET_B4420QDS
20 bool "Support B4420QDS"
25 config TARGET_B4860QDS
26 bool "Support B4860QDS"
31 config TARGET_BSC9131RDB
32 bool "Support BSC9131RDB"
36 config TARGET_BSC9132QDS
37 bool "Support BSC9132QDS"
41 config TARGET_C29XPCIE
42 bool "Support C29XPCIE"
49 bool "Support P3041DS"
54 bool "Support P4080DS"
59 bool "Support P5020DS"
64 bool "Support P5040DS"
68 config TARGET_MPC8536DS
69 bool "Support MPC8536DS"
71 # Use DDR3 controller with DDR2 DIMMs on this board
72 select SYS_FSL_DDRC_GEN3
74 config TARGET_MPC8540ADS
75 bool "Support MPC8540ADS"
78 config TARGET_MPC8541CDS
79 bool "Support MPC8541CDS"
82 config TARGET_MPC8544DS
83 bool "Support MPC8544DS"
86 config TARGET_MPC8548CDS
87 bool "Support MPC8548CDS"
90 config TARGET_MPC8555CDS
91 bool "Support MPC8555CDS"
94 config TARGET_MPC8560ADS
95 bool "Support MPC8560ADS"
98 config TARGET_MPC8568MDS
99 bool "Support MPC8568MDS"
102 config TARGET_MPC8569MDS
103 bool "Support MPC8569MDS"
106 config TARGET_MPC8572DS
107 bool "Support MPC8572DS"
109 # Use DDR3 controller with DDR2 DIMMs on this board
110 select SYS_FSL_DDRC_GEN3
112 config TARGET_P1010RDB_PA
113 bool "Support P1010RDB_PA"
118 config TARGET_P1010RDB_PB
119 bool "Support P1010RDB_PB"
124 config TARGET_P1022DS
125 bool "Support P1022DS"
130 config TARGET_P1023RDB
131 bool "Support P1023RDB"
134 config TARGET_P1020MBG
135 bool "Support P1020MBG-PC"
140 config TARGET_P1020RDB_PC
141 bool "Support P1020RDB-PC"
146 config TARGET_P1020RDB_PD
147 bool "Support P1020RDB-PD"
152 config TARGET_P1020UTM
153 bool "Support P1020UTM"
158 config TARGET_P1021RDB
159 bool "Support P1021RDB"
164 config TARGET_P1024RDB
165 bool "Support P1024RDB"
170 config TARGET_P1025RDB
171 bool "Support P1025RDB"
176 config TARGET_P2020RDB
177 bool "Support P2020RDB-PC"
183 bool "Support p1_twr"
186 config TARGET_P2041RDB
187 bool "Support P2041RDB"
191 config TARGET_QEMU_PPCE500
192 bool "Support qemu-ppce500"
193 select ARCH_QEMU_E500
196 config TARGET_T1024QDS
197 bool "Support T1024QDS"
202 config TARGET_T1023RDB
203 bool "Support T1023RDB"
208 config TARGET_T1024RDB
209 bool "Support T1024RDB"
214 config TARGET_T1040QDS
215 bool "Support T1040QDS"
219 config TARGET_T1040RDB
220 bool "Support T1040RDB"
225 config TARGET_T1040D4RDB
226 bool "Support T1040D4RDB"
231 config TARGET_T1042RDB
232 bool "Support T1042RDB"
237 config TARGET_T1042D4RDB
238 bool "Support T1042D4RDB"
243 config TARGET_T1042RDB_PI
244 bool "Support T1042RDB_PI"
249 config TARGET_T2080QDS
250 bool "Support T2080QDS"
255 config TARGET_T2080RDB
256 bool "Support T2080RDB"
261 config TARGET_T2081QDS
262 bool "Support T2081QDS"
267 config TARGET_T4160QDS
268 bool "Support T4160QDS"
273 config TARGET_T4160RDB
274 bool "Support T4160RDB"
279 config TARGET_T4240QDS
280 bool "Support T4240QDS"
285 config TARGET_T4240RDB
286 bool "Support T4240RDB"
291 config TARGET_CONTROLCENTERD
292 bool "Support controlcenterd"
295 config TARGET_KMP204X
296 bool "Support kmp204x"
300 config TARGET_XPEDITE520X
301 bool "Support xpedite520x"
304 config TARGET_XPEDITE537X
305 bool "Support xpedite537x"
307 # Use DDR3 controller with DDR2 DIMMs on this board
308 select SYS_FSL_DDRC_GEN3
310 config TARGET_XPEDITE550X
311 bool "Support xpedite550x"
314 config TARGET_UCP1020
315 bool "Support uCP1020"
318 config TARGET_CYRUS_P5020
319 bool "Support Varisys Cyrus P5020"
323 config TARGET_CYRUS_P5040
324 bool "Support Varisys Cyrus P5040"
334 select SYS_FSL_HAS_DDR3
335 select SYS_FSL_HAS_SEC
336 select SYS_FSL_SEC_BE
337 select SYS_FSL_SEC_COMPAT_4
343 select SYS_FSL_HAS_DDR3
344 select SYS_FSL_HAS_SEC
345 select SYS_FSL_SEC_BE
346 select SYS_FSL_SEC_COMPAT_4
351 select SYS_FSL_ERRATUM_ESDHC111
352 select SYS_FSL_HAS_DDR3
353 select SYS_FSL_HAS_SEC
354 select SYS_FSL_SEC_BE
355 select SYS_FSL_SEC_COMPAT_4
360 select SYS_FSL_ERRATUM_ESDHC111
361 select SYS_FSL_HAS_DDR3
362 select SYS_FSL_HAS_SEC
363 select SYS_FSL_SEC_BE
364 select SYS_FSL_SEC_COMPAT_4
365 select SYS_PPC_E500_USE_DEBUG_TLB
370 select SYS_FSL_ERRATUM_ESDHC111
371 select SYS_FSL_HAS_DDR3
372 select SYS_FSL_HAS_SEC
373 select SYS_FSL_SEC_BE
374 select SYS_FSL_SEC_COMPAT_6
375 select SYS_PPC_E500_USE_DEBUG_TLB
380 select SYS_FSL_HAS_DDR2
381 select SYS_FSL_HAS_DDR3
382 select SYS_FSL_HAS_SEC
383 select SYS_FSL_SEC_BE
384 select SYS_FSL_SEC_COMPAT_2
385 select SYS_PPC_E500_USE_DEBUG_TLB
390 select SYS_FSL_HAS_DDR1
395 select SYS_FSL_HAS_DDR1
396 select SYS_FSL_HAS_SEC
397 select SYS_FSL_SEC_BE
398 select SYS_FSL_SEC_COMPAT_2
403 select SYS_FSL_HAS_DDR2
404 select SYS_FSL_HAS_SEC
405 select SYS_FSL_SEC_BE
406 select SYS_FSL_SEC_COMPAT_2
407 select SYS_PPC_E500_USE_DEBUG_TLB
412 select SYS_FSL_HAS_DDR2
413 select SYS_FSL_HAS_DDR1
414 select SYS_FSL_HAS_SEC
415 select SYS_FSL_SEC_BE
416 select SYS_FSL_SEC_COMPAT_2
417 select SYS_PPC_E500_USE_DEBUG_TLB
422 select SYS_FSL_HAS_DDR1
423 select SYS_FSL_HAS_SEC
424 select SYS_FSL_SEC_BE
425 select SYS_FSL_SEC_COMPAT_2
430 select SYS_FSL_HAS_DDR1
435 select SYS_FSL_HAS_DDR2
436 select SYS_FSL_HAS_SEC
437 select SYS_FSL_SEC_BE
438 select SYS_FSL_SEC_COMPAT_2
443 select SYS_FSL_HAS_DDR3
444 select SYS_FSL_HAS_SEC
445 select SYS_FSL_SEC_BE
446 select SYS_FSL_SEC_COMPAT_2
451 select SYS_FSL_HAS_DDR2
452 select SYS_FSL_HAS_DDR3
453 select SYS_FSL_HAS_SEC
454 select SYS_FSL_SEC_BE
455 select SYS_FSL_SEC_COMPAT_2
456 select SYS_PPC_E500_USE_DEBUG_TLB
461 select SYS_FSL_ERRATUM_ESDHC111
462 select SYS_FSL_HAS_DDR3
463 select SYS_FSL_HAS_SEC
464 select SYS_FSL_SEC_BE
465 select SYS_FSL_SEC_COMPAT_4
466 select SYS_PPC_E500_USE_DEBUG_TLB
471 select SYS_FSL_ERRATUM_ESDHC111
472 select SYS_FSL_HAS_DDR3
473 select SYS_FSL_HAS_SEC
474 select SYS_FSL_SEC_BE
475 select SYS_FSL_SEC_COMPAT_2
476 select SYS_PPC_E500_USE_DEBUG_TLB
481 select SYS_FSL_ERRATUM_ESDHC111
482 select SYS_FSL_HAS_DDR3
483 select SYS_FSL_HAS_SEC
484 select SYS_FSL_SEC_BE
485 select SYS_FSL_SEC_COMPAT_2
486 select SYS_PPC_E500_USE_DEBUG_TLB
491 select SYS_FSL_ERRATUM_ESDHC111
492 select SYS_FSL_HAS_DDR3
493 select SYS_FSL_HAS_SEC
494 select SYS_FSL_SEC_BE
495 select SYS_FSL_SEC_COMPAT_2
496 select SYS_PPC_E500_USE_DEBUG_TLB
501 select SYS_FSL_ERRATUM_ESDHC111
502 select SYS_FSL_HAS_DDR3
503 select SYS_FSL_HAS_SEC
504 select SYS_FSL_SEC_BE
505 select SYS_FSL_SEC_COMPAT_2
506 select SYS_PPC_E500_USE_DEBUG_TLB
511 select SYS_FSL_HAS_DDR3
512 select SYS_FSL_HAS_SEC
513 select SYS_FSL_SEC_BE
514 select SYS_FSL_SEC_COMPAT_4
519 select SYS_FSL_ERRATUM_ESDHC111
520 select SYS_FSL_HAS_DDR3
521 select SYS_FSL_HAS_SEC
522 select SYS_FSL_SEC_BE
523 select SYS_FSL_SEC_COMPAT_2
524 select SYS_PPC_E500_USE_DEBUG_TLB
529 select SYS_FSL_ERRATUM_ESDHC111
530 select SYS_FSL_HAS_DDR3
531 select SYS_FSL_HAS_SEC
532 select SYS_FSL_SEC_BE
533 select SYS_FSL_SEC_COMPAT_2
534 select SYS_PPC_E500_USE_DEBUG_TLB
539 select SYS_FSL_ERRATUM_ESDHC111
540 select SYS_FSL_ERRATUM_ESDHC_A001
541 select SYS_FSL_HAS_DDR3
542 select SYS_FSL_HAS_SEC
543 select SYS_FSL_SEC_BE
544 select SYS_FSL_SEC_COMPAT_2
545 select SYS_PPC_E500_USE_DEBUG_TLB
551 select SYS_FSL_ERRATUM_ESDHC111
552 select SYS_FSL_HAS_DDR3
553 select SYS_FSL_HAS_SEC
554 select SYS_FSL_SEC_BE
555 select SYS_FSL_SEC_COMPAT_4
561 select SYS_FSL_ERRATUM_ESDHC111
562 select SYS_FSL_HAS_DDR3
563 select SYS_FSL_HAS_SEC
564 select SYS_FSL_SEC_BE
565 select SYS_FSL_SEC_COMPAT_4
571 select SYS_FSL_ERRATUM_ESDHC111
572 select SYS_FSL_ERRATUM_ESDHC13
573 select SYS_FSL_ERRATUM_ESDHC135
574 select SYS_FSL_HAS_DDR3
575 select SYS_FSL_HAS_SEC
576 select SYS_FSL_SEC_BE
577 select SYS_FSL_SEC_COMPAT_4
583 select SYS_FSL_ERRATUM_ESDHC111
584 select SYS_FSL_HAS_DDR3
585 select SYS_FSL_HAS_SEC
586 select SYS_FSL_SEC_BE
587 select SYS_FSL_SEC_COMPAT_4
593 select SYS_FSL_ERRATUM_ESDHC111
594 select SYS_FSL_HAS_DDR3
595 select SYS_FSL_HAS_SEC
596 select SYS_FSL_SEC_BE
597 select SYS_FSL_SEC_COMPAT_4
599 config ARCH_QEMU_E500
606 select SYS_FSL_ERRATUM_ESDHC111
607 select SYS_FSL_HAS_DDR3
608 select SYS_FSL_HAS_DDR4
609 select SYS_FSL_HAS_SEC
610 select SYS_FSL_SEC_BE
611 select SYS_FSL_SEC_COMPAT_5
617 select SYS_FSL_ERRATUM_ESDHC111
618 select SYS_FSL_HAS_DDR3
619 select SYS_FSL_HAS_DDR4
620 select SYS_FSL_HAS_SEC
621 select SYS_FSL_SEC_BE
622 select SYS_FSL_SEC_COMPAT_5
628 select SYS_FSL_ERRATUM_ESDHC111
629 select SYS_FSL_HAS_DDR3
630 select SYS_FSL_HAS_DDR4
631 select SYS_FSL_HAS_SEC
632 select SYS_FSL_SEC_BE
633 select SYS_FSL_SEC_COMPAT_5
639 select SYS_FSL_ERRATUM_ESDHC111
640 select SYS_FSL_HAS_DDR3
641 select SYS_FSL_HAS_DDR4
642 select SYS_FSL_HAS_SEC
643 select SYS_FSL_SEC_BE
644 select SYS_FSL_SEC_COMPAT_5
650 select SYS_FSL_ERRATUM_ESDHC111
651 select SYS_FSL_HAS_DDR3
652 select SYS_FSL_HAS_SEC
653 select SYS_FSL_SEC_BE
654 select SYS_FSL_SEC_COMPAT_4
660 select SYS_FSL_ERRATUM_ESDHC111
661 select SYS_FSL_HAS_DDR3
662 select SYS_FSL_HAS_SEC
663 select SYS_FSL_SEC_BE
664 select SYS_FSL_SEC_COMPAT_4
670 select SYS_FSL_HAS_DDR3
671 select SYS_FSL_HAS_SEC
672 select SYS_FSL_SEC_BE
673 select SYS_FSL_SEC_COMPAT_4
679 select SYS_FSL_HAS_DDR3
680 select SYS_FSL_HAS_SEC
681 select SYS_FSL_SEC_BE
682 select SYS_FSL_SEC_COMPAT_4
692 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
697 Enble PowerPC E500MC core
702 Use Freescale common code for Local Access Window
707 Enable Freescale Secure Boot feature. Normally selected
708 by defconfig. If unsure, do not change.
711 int "Maximum number of CPUs permitted for MPC85xx"
712 default 12 if ARCH_T4240
713 default 8 if ARCH_P4080 || \
715 default 4 if ARCH_B4860 || \
723 default 2 if ARCH_B4420 || \
738 Set this number to the maximum number of possible CPUs in the SoC.
739 SoCs may have multiple clusters with each cluster may have multiple
740 ports. If some ports are reserved but higher ports are used for
741 cores, count the reserved ports. This will allocate enough memory
742 in spin table to properly handle all cores.
744 config SYS_CCSRBAR_DEFAULT
745 hex "Default CCSRBAR address"
746 default 0xff700000 if ARCH_BSC9131 || \
767 default 0xff600000 if ARCH_P1023
768 default 0xfe000000 if ARCH_B4420 || \
783 default 0xe0000000 if ARCH_QEMU_E500
785 Default value of CCSRBAR comes from power-on-reset. It
786 is fixed on each SoC. Some SoCs can have different value
787 if changed by pre-boot regime. The value here must match
788 the current value in SoC. If not sure, do not change.
790 config SYS_FSL_NUM_LAWS
791 int "Number of local access windows"
793 default 32 if ARCH_B4420 || \
804 default 16 if ARCH_T1023 || \
808 default 12 if ARCH_BSC9131 || \
822 default 10 if ARCH_MPC8544 || \
826 default 8 if ARCH_MPC8540 || \
831 Number of local access windows. This is fixed per SoC.
832 If not sure, do not change.
834 config SYS_NUM_TLBCAMS
835 int "Number of TLB CAM entries"
839 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
840 16 for other E500 SoCs.
842 config SYS_PPC_E500_USE_DEBUG_TLB
845 config SYS_PPC_E500_DEBUG_TLB
846 int "Temporary TLB entry for external debugger"
847 depends on SYS_PPC_E500_USE_DEBUG_TLB
848 default 0 if ARCH_MPC8544 || ARCH_MPC8548
849 default 1 if ARCH_MPC8536
850 default 2 if ARCH_MPC8572 || \
858 default 3 if ARCH_P1010 || \
862 Select a temporary TLB entry to be used during boot to work
863 around limitations in e500v1 and e500v2 external debugger
864 support. This reduces the portions of the boot code where
865 breakpoints and single stepping do not work. The value of this
866 symbol should be set to the TLB1 entry to be used for this
867 purpose. If unsure, do not change.
869 source "board/freescale/b4860qds/Kconfig"
870 source "board/freescale/bsc9131rdb/Kconfig"
871 source "board/freescale/bsc9132qds/Kconfig"
872 source "board/freescale/c29xpcie/Kconfig"
873 source "board/freescale/corenet_ds/Kconfig"
874 source "board/freescale/mpc8536ds/Kconfig"
875 source "board/freescale/mpc8540ads/Kconfig"
876 source "board/freescale/mpc8541cds/Kconfig"
877 source "board/freescale/mpc8544ds/Kconfig"
878 source "board/freescale/mpc8548cds/Kconfig"
879 source "board/freescale/mpc8555cds/Kconfig"
880 source "board/freescale/mpc8560ads/Kconfig"
881 source "board/freescale/mpc8568mds/Kconfig"
882 source "board/freescale/mpc8569mds/Kconfig"
883 source "board/freescale/mpc8572ds/Kconfig"
884 source "board/freescale/p1010rdb/Kconfig"
885 source "board/freescale/p1022ds/Kconfig"
886 source "board/freescale/p1023rdb/Kconfig"
887 source "board/freescale/p1_p2_rdb_pc/Kconfig"
888 source "board/freescale/p1_twr/Kconfig"
889 source "board/freescale/p2041rdb/Kconfig"
890 source "board/freescale/qemu-ppce500/Kconfig"
891 source "board/freescale/t102xqds/Kconfig"
892 source "board/freescale/t102xrdb/Kconfig"
893 source "board/freescale/t1040qds/Kconfig"
894 source "board/freescale/t104xrdb/Kconfig"
895 source "board/freescale/t208xqds/Kconfig"
896 source "board/freescale/t208xrdb/Kconfig"
897 source "board/freescale/t4qds/Kconfig"
898 source "board/freescale/t4rdb/Kconfig"
899 source "board/gdsys/p1022/Kconfig"
900 source "board/keymile/kmp204x/Kconfig"
901 source "board/sbc8548/Kconfig"
902 source "board/socrates/Kconfig"
903 source "board/varisys/cyrus/Kconfig"
904 source "board/xes/xpedite520x/Kconfig"
905 source "board/xes/xpedite537x/Kconfig"
906 source "board/xes/xpedite550x/Kconfig"
907 source "board/Arcturus/ucp1020/Kconfig"