12 bool "Support sbc8548"
15 config TARGET_SOCRATES
16 bool "Support socrates"
19 config TARGET_B4420QDS
20 bool "Support B4420QDS"
25 config TARGET_B4860QDS
26 bool "Support B4860QDS"
31 config TARGET_BSC9131RDB
32 bool "Support BSC9131RDB"
36 config TARGET_BSC9132QDS
37 bool "Support BSC9132QDS"
41 config TARGET_C29XPCIE
42 bool "Support C29XPCIE"
49 bool "Support P3041DS"
54 bool "Support P4080DS"
59 bool "Support P5020DS"
64 bool "Support P5040DS"
68 config TARGET_MPC8536DS
69 bool "Support MPC8536DS"
71 # Use DDR3 controller with DDR2 DIMMs on this board
72 select SYS_FSL_DDRC_GEN3
74 config TARGET_MPC8540ADS
75 bool "Support MPC8540ADS"
78 config TARGET_MPC8541CDS
79 bool "Support MPC8541CDS"
82 config TARGET_MPC8544DS
83 bool "Support MPC8544DS"
86 config TARGET_MPC8548CDS
87 bool "Support MPC8548CDS"
90 config TARGET_MPC8555CDS
91 bool "Support MPC8555CDS"
94 config TARGET_MPC8560ADS
95 bool "Support MPC8560ADS"
98 config TARGET_MPC8568MDS
99 bool "Support MPC8568MDS"
102 config TARGET_MPC8569MDS
103 bool "Support MPC8569MDS"
106 config TARGET_MPC8572DS
107 bool "Support MPC8572DS"
109 # Use DDR3 controller with DDR2 DIMMs on this board
110 select SYS_FSL_DDRC_GEN3
112 config TARGET_P1010RDB_PA
113 bool "Support P1010RDB_PA"
118 config TARGET_P1010RDB_PB
119 bool "Support P1010RDB_PB"
124 config TARGET_P1022DS
125 bool "Support P1022DS"
130 config TARGET_P1023RDB
131 bool "Support P1023RDB"
134 config TARGET_P1020MBG
135 bool "Support P1020MBG-PC"
140 config TARGET_P1020RDB_PC
141 bool "Support P1020RDB-PC"
146 config TARGET_P1020RDB_PD
147 bool "Support P1020RDB-PD"
152 config TARGET_P1020UTM
153 bool "Support P1020UTM"
158 config TARGET_P1021RDB
159 bool "Support P1021RDB"
164 config TARGET_P1024RDB
165 bool "Support P1024RDB"
170 config TARGET_P1025RDB
171 bool "Support P1025RDB"
176 config TARGET_P2020RDB
177 bool "Support P2020RDB-PC"
183 bool "Support p1_twr"
186 config TARGET_P2041RDB
187 bool "Support P2041RDB"
191 config TARGET_QEMU_PPCE500
192 bool "Support qemu-ppce500"
193 select ARCH_QEMU_E500
196 config TARGET_T1024QDS
197 bool "Support T1024QDS"
202 config TARGET_T1023RDB
203 bool "Support T1023RDB"
208 config TARGET_T1024RDB
209 bool "Support T1024RDB"
214 config TARGET_T1040QDS
215 bool "Support T1040QDS"
219 config TARGET_T1040RDB
220 bool "Support T1040RDB"
225 config TARGET_T1040D4RDB
226 bool "Support T1040D4RDB"
231 config TARGET_T1042RDB
232 bool "Support T1042RDB"
237 config TARGET_T1042D4RDB
238 bool "Support T1042D4RDB"
243 config TARGET_T1042RDB_PI
244 bool "Support T1042RDB_PI"
249 config TARGET_T2080QDS
250 bool "Support T2080QDS"
255 config TARGET_T2080RDB
256 bool "Support T2080RDB"
261 config TARGET_T2081QDS
262 bool "Support T2081QDS"
267 config TARGET_T4160QDS
268 bool "Support T4160QDS"
273 config TARGET_T4160RDB
274 bool "Support T4160RDB"
279 config TARGET_T4240QDS
280 bool "Support T4240QDS"
285 config TARGET_T4240RDB
286 bool "Support T4240RDB"
291 config TARGET_CONTROLCENTERD
292 bool "Support controlcenterd"
295 config TARGET_KMP204X
296 bool "Support kmp204x"
300 config TARGET_XPEDITE520X
301 bool "Support xpedite520x"
304 config TARGET_XPEDITE537X
305 bool "Support xpedite537x"
307 # Use DDR3 controller with DDR2 DIMMs on this board
308 select SYS_FSL_DDRC_GEN3
310 config TARGET_XPEDITE550X
311 bool "Support xpedite550x"
314 config TARGET_UCP1020
315 bool "Support uCP1020"
318 config TARGET_CYRUS_P5020
319 bool "Support Varisys Cyrus P5020"
323 config TARGET_CYRUS_P5040
324 bool "Support Varisys Cyrus P5040"
334 select SYS_FSL_HAS_DDR3
335 select SYS_FSL_HAS_SEC
336 select SYS_FSL_SEC_BE
337 select SYS_FSL_SEC_COMPAT_4
343 select SYS_FSL_HAS_DDR3
344 select SYS_FSL_HAS_SEC
345 select SYS_FSL_SEC_BE
346 select SYS_FSL_SEC_COMPAT_4
351 select SYS_FSL_HAS_DDR3
352 select SYS_FSL_HAS_SEC
353 select SYS_FSL_SEC_BE
354 select SYS_FSL_SEC_COMPAT_4
359 select SYS_FSL_HAS_DDR3
360 select SYS_FSL_HAS_SEC
361 select SYS_FSL_SEC_BE
362 select SYS_FSL_SEC_COMPAT_4
363 select SYS_PPC_E500_USE_DEBUG_TLB
368 select SYS_FSL_HAS_DDR3
369 select SYS_FSL_HAS_SEC
370 select SYS_FSL_SEC_BE
371 select SYS_FSL_SEC_COMPAT_6
372 select SYS_PPC_E500_USE_DEBUG_TLB
377 select SYS_FSL_HAS_DDR2
378 select SYS_FSL_HAS_DDR3
379 select SYS_FSL_HAS_SEC
380 select SYS_FSL_SEC_BE
381 select SYS_FSL_SEC_COMPAT_2
382 select SYS_PPC_E500_USE_DEBUG_TLB
387 select SYS_FSL_HAS_DDR1
392 select SYS_FSL_HAS_DDR1
393 select SYS_FSL_HAS_SEC
394 select SYS_FSL_SEC_BE
395 select SYS_FSL_SEC_COMPAT_2
400 select SYS_FSL_HAS_DDR2
401 select SYS_FSL_HAS_SEC
402 select SYS_FSL_SEC_BE
403 select SYS_FSL_SEC_COMPAT_2
404 select SYS_PPC_E500_USE_DEBUG_TLB
409 select SYS_FSL_HAS_DDR2
410 select SYS_FSL_HAS_DDR1
411 select SYS_FSL_HAS_SEC
412 select SYS_FSL_SEC_BE
413 select SYS_FSL_SEC_COMPAT_2
414 select SYS_PPC_E500_USE_DEBUG_TLB
419 select SYS_FSL_HAS_DDR1
420 select SYS_FSL_HAS_SEC
421 select SYS_FSL_SEC_BE
422 select SYS_FSL_SEC_COMPAT_2
427 select SYS_FSL_HAS_DDR1
432 select SYS_FSL_HAS_DDR2
433 select SYS_FSL_HAS_SEC
434 select SYS_FSL_SEC_BE
435 select SYS_FSL_SEC_COMPAT_2
440 select SYS_FSL_HAS_DDR3
441 select SYS_FSL_HAS_SEC
442 select SYS_FSL_SEC_BE
443 select SYS_FSL_SEC_COMPAT_2
448 select SYS_FSL_HAS_DDR2
449 select SYS_FSL_HAS_DDR3
450 select SYS_FSL_HAS_SEC
451 select SYS_FSL_SEC_BE
452 select SYS_FSL_SEC_COMPAT_2
453 select SYS_PPC_E500_USE_DEBUG_TLB
458 select SYS_FSL_HAS_DDR3
459 select SYS_FSL_HAS_SEC
460 select SYS_FSL_SEC_BE
461 select SYS_FSL_SEC_COMPAT_4
462 select SYS_PPC_E500_USE_DEBUG_TLB
467 select SYS_FSL_HAS_DDR3
468 select SYS_FSL_HAS_SEC
469 select SYS_FSL_SEC_BE
470 select SYS_FSL_SEC_COMPAT_2
471 select SYS_PPC_E500_USE_DEBUG_TLB
476 select SYS_FSL_HAS_DDR3
477 select SYS_FSL_HAS_SEC
478 select SYS_FSL_SEC_BE
479 select SYS_FSL_SEC_COMPAT_2
480 select SYS_PPC_E500_USE_DEBUG_TLB
485 select SYS_FSL_HAS_DDR3
486 select SYS_FSL_HAS_SEC
487 select SYS_FSL_SEC_BE
488 select SYS_FSL_SEC_COMPAT_2
489 select SYS_PPC_E500_USE_DEBUG_TLB
494 select SYS_FSL_HAS_DDR3
495 select SYS_FSL_HAS_SEC
496 select SYS_FSL_SEC_BE
497 select SYS_FSL_SEC_COMPAT_2
498 select SYS_PPC_E500_USE_DEBUG_TLB
503 select SYS_FSL_HAS_DDR3
504 select SYS_FSL_HAS_SEC
505 select SYS_FSL_SEC_BE
506 select SYS_FSL_SEC_COMPAT_4
511 select SYS_FSL_HAS_DDR3
512 select SYS_FSL_HAS_SEC
513 select SYS_FSL_SEC_BE
514 select SYS_FSL_SEC_COMPAT_2
515 select SYS_PPC_E500_USE_DEBUG_TLB
520 select SYS_FSL_HAS_DDR3
521 select SYS_FSL_HAS_SEC
522 select SYS_FSL_SEC_BE
523 select SYS_FSL_SEC_COMPAT_2
524 select SYS_PPC_E500_USE_DEBUG_TLB
529 select SYS_FSL_HAS_DDR3
530 select SYS_FSL_HAS_SEC
531 select SYS_FSL_SEC_BE
532 select SYS_FSL_SEC_COMPAT_2
533 select SYS_PPC_E500_USE_DEBUG_TLB
539 select SYS_FSL_HAS_DDR3
540 select SYS_FSL_HAS_SEC
541 select SYS_FSL_SEC_BE
542 select SYS_FSL_SEC_COMPAT_4
548 select SYS_FSL_HAS_DDR3
549 select SYS_FSL_HAS_SEC
550 select SYS_FSL_SEC_BE
551 select SYS_FSL_SEC_COMPAT_4
557 select SYS_FSL_HAS_DDR3
558 select SYS_FSL_HAS_SEC
559 select SYS_FSL_SEC_BE
560 select SYS_FSL_SEC_COMPAT_4
566 select SYS_FSL_HAS_DDR3
567 select SYS_FSL_HAS_SEC
568 select SYS_FSL_SEC_BE
569 select SYS_FSL_SEC_COMPAT_4
575 select SYS_FSL_HAS_DDR3
576 select SYS_FSL_HAS_SEC
577 select SYS_FSL_SEC_BE
578 select SYS_FSL_SEC_COMPAT_4
580 config ARCH_QEMU_E500
587 select SYS_FSL_HAS_DDR3
588 select SYS_FSL_HAS_DDR4
589 select SYS_FSL_HAS_SEC
590 select SYS_FSL_SEC_BE
591 select SYS_FSL_SEC_COMPAT_5
597 select SYS_FSL_HAS_DDR3
598 select SYS_FSL_HAS_DDR4
599 select SYS_FSL_HAS_SEC
600 select SYS_FSL_SEC_BE
601 select SYS_FSL_SEC_COMPAT_5
607 select SYS_FSL_HAS_DDR3
608 select SYS_FSL_HAS_DDR4
609 select SYS_FSL_HAS_SEC
610 select SYS_FSL_SEC_BE
611 select SYS_FSL_SEC_COMPAT_5
617 select SYS_FSL_HAS_DDR3
618 select SYS_FSL_HAS_DDR4
619 select SYS_FSL_HAS_SEC
620 select SYS_FSL_SEC_BE
621 select SYS_FSL_SEC_COMPAT_5
627 select SYS_FSL_HAS_DDR3
628 select SYS_FSL_HAS_SEC
629 select SYS_FSL_SEC_BE
630 select SYS_FSL_SEC_COMPAT_4
636 select SYS_FSL_HAS_DDR3
637 select SYS_FSL_HAS_SEC
638 select SYS_FSL_SEC_BE
639 select SYS_FSL_SEC_COMPAT_4
645 select SYS_FSL_HAS_DDR3
646 select SYS_FSL_HAS_SEC
647 select SYS_FSL_SEC_BE
648 select SYS_FSL_SEC_COMPAT_4
654 select SYS_FSL_HAS_DDR3
655 select SYS_FSL_HAS_SEC
656 select SYS_FSL_SEC_BE
657 select SYS_FSL_SEC_COMPAT_4
667 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
672 Enble PowerPC E500MC core
677 Use Freescale common code for Local Access Window
682 Enable Freescale Secure Boot feature. Normally selected
683 by defconfig. If unsure, do not change.
686 int "Maximum number of CPUs permitted for MPC85xx"
687 default 12 if ARCH_T4240
688 default 8 if ARCH_P4080 || \
690 default 4 if ARCH_B4860 || \
698 default 2 if ARCH_B4420 || \
713 Set this number to the maximum number of possible CPUs in the SoC.
714 SoCs may have multiple clusters with each cluster may have multiple
715 ports. If some ports are reserved but higher ports are used for
716 cores, count the reserved ports. This will allocate enough memory
717 in spin table to properly handle all cores.
719 config SYS_CCSRBAR_DEFAULT
720 hex "Default CCSRBAR address"
721 default 0xff700000 if ARCH_BSC9131 || \
742 default 0xff600000 if ARCH_P1023
743 default 0xfe000000 if ARCH_B4420 || \
758 default 0xe0000000 if ARCH_QEMU_E500
760 Default value of CCSRBAR comes from power-on-reset. It
761 is fixed on each SoC. Some SoCs can have different value
762 if changed by pre-boot regime. The value here must match
763 the current value in SoC. If not sure, do not change.
765 config SYS_FSL_NUM_LAWS
766 int "Number of local access windows"
768 default 32 if ARCH_B4420 || \
779 default 16 if ARCH_T1023 || \
783 default 12 if ARCH_BSC9131 || \
797 default 10 if ARCH_MPC8544 || \
801 default 8 if ARCH_MPC8540 || \
806 Number of local access windows. This is fixed per SoC.
807 If not sure, do not change.
809 config SYS_NUM_TLBCAMS
810 int "Number of TLB CAM entries"
814 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
815 16 for other E500 SoCs.
817 config SYS_PPC_E500_USE_DEBUG_TLB
820 config SYS_PPC_E500_DEBUG_TLB
821 int "Temporary TLB entry for external debugger"
822 depends on SYS_PPC_E500_USE_DEBUG_TLB
823 default 0 if ARCH_MPC8544 || ARCH_MPC8548
824 default 1 if ARCH_MPC8536
825 default 2 if ARCH_MPC8572 || \
833 default 3 if ARCH_P1010 || \
837 Select a temporary TLB entry to be used during boot to work
838 around limitations in e500v1 and e500v2 external debugger
839 support. This reduces the portions of the boot code where
840 breakpoints and single stepping do not work. The value of this
841 symbol should be set to the TLB1 entry to be used for this
842 purpose. If unsure, do not change.
844 source "board/freescale/b4860qds/Kconfig"
845 source "board/freescale/bsc9131rdb/Kconfig"
846 source "board/freescale/bsc9132qds/Kconfig"
847 source "board/freescale/c29xpcie/Kconfig"
848 source "board/freescale/corenet_ds/Kconfig"
849 source "board/freescale/mpc8536ds/Kconfig"
850 source "board/freescale/mpc8540ads/Kconfig"
851 source "board/freescale/mpc8541cds/Kconfig"
852 source "board/freescale/mpc8544ds/Kconfig"
853 source "board/freescale/mpc8548cds/Kconfig"
854 source "board/freescale/mpc8555cds/Kconfig"
855 source "board/freescale/mpc8560ads/Kconfig"
856 source "board/freescale/mpc8568mds/Kconfig"
857 source "board/freescale/mpc8569mds/Kconfig"
858 source "board/freescale/mpc8572ds/Kconfig"
859 source "board/freescale/p1010rdb/Kconfig"
860 source "board/freescale/p1022ds/Kconfig"
861 source "board/freescale/p1023rdb/Kconfig"
862 source "board/freescale/p1_p2_rdb_pc/Kconfig"
863 source "board/freescale/p1_twr/Kconfig"
864 source "board/freescale/p2041rdb/Kconfig"
865 source "board/freescale/qemu-ppce500/Kconfig"
866 source "board/freescale/t102xqds/Kconfig"
867 source "board/freescale/t102xrdb/Kconfig"
868 source "board/freescale/t1040qds/Kconfig"
869 source "board/freescale/t104xrdb/Kconfig"
870 source "board/freescale/t208xqds/Kconfig"
871 source "board/freescale/t208xrdb/Kconfig"
872 source "board/freescale/t4qds/Kconfig"
873 source "board/freescale/t4rdb/Kconfig"
874 source "board/gdsys/p1022/Kconfig"
875 source "board/keymile/kmp204x/Kconfig"
876 source "board/sbc8548/Kconfig"
877 source "board/socrates/Kconfig"
878 source "board/varisys/cyrus/Kconfig"
879 source "board/xes/xpedite520x/Kconfig"
880 source "board/xes/xpedite537x/Kconfig"
881 source "board/xes/xpedite550x/Kconfig"
882 source "board/Arcturus/ucp1020/Kconfig"