2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 #include <asm/fsl_ifc.h>
37 #include <asm/fsl_law.h>
38 #include <asm/fsl_lbc.h>
40 #include <asm/processor.h>
41 #include <asm/fsl_ddr_sdram.h>
43 DECLARE_GLOBAL_DATA_PTR;
46 * Default board reset function
53 void board_reset(void) __attribute__((weak, alias("__board_reset")));
62 char buf1[32], buf2[32];
63 #if defined(CONFIG_DDR_CLK_FREQ) || \
64 (defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2))
65 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
66 #endif /* CONFIG_FSL_CORENET */
67 #ifdef CONFIG_DDR_CLK_FREQ
68 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
69 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
71 #ifdef CONFIG_FSL_CORENET
73 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
74 ddr_sync = 0; /* only async mode is supported */
76 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
77 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
78 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
81 #endif /* CONFIG_FSL_CORENET */
82 #endif /* CONFIG_DDR_CLK_FREQ */
83 unsigned int i, core, nr_cores = cpu_numcores();
84 u32 mask = cpu_mask();
90 if (cpu_numcores() > 1) {
92 puts("Unicore software on multiprocessor system!!\n"
93 "To enable mutlticore build define CONFIG_MP\n");
95 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
96 printf("CPU%d: ", pic->whoami);
104 if (IS_E_PROCESSOR(svr))
107 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
111 major = PVR_MAJ(pvr);
112 minor = PVR_MIN(pvr);
116 case PVR_VER_E500_V1:
117 case PVR_VER_E500_V2:
134 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
136 if (nr_cores > CONFIG_MAX_CPUS) {
137 panic("\nUnexpected number of cores: %d, max is %d\n",
138 nr_cores, CONFIG_MAX_CPUS);
141 get_sys_info(&sysinfo);
143 puts("Clock Configuration:");
144 for_each_cpu(i, core, nr_cores, mask) {
147 printf("CPU%d:%-4s MHz, ", core,
148 strmhz(buf1, sysinfo.freqProcessor[core]));
150 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
152 #ifdef CONFIG_FSL_CORENET
154 printf(" DDR:%-4s MHz (%s MT/s data rate) "
156 strmhz(buf1, sysinfo.freqDDRBus/2),
157 strmhz(buf2, sysinfo.freqDDRBus));
159 printf(" DDR:%-4s MHz (%s MT/s data rate) "
161 strmhz(buf1, sysinfo.freqDDRBus/2),
162 strmhz(buf2, sysinfo.freqDDRBus));
167 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
168 strmhz(buf1, sysinfo.freqDDRBus/2),
169 strmhz(buf2, sysinfo.freqDDRBus));
172 printf(" DDR:%-4s MHz (%s MT/s data rate) "
174 strmhz(buf1, sysinfo.freqDDRBus/2),
175 strmhz(buf2, sysinfo.freqDDRBus));
178 printf(" DDR:%-4s MHz (%s MT/s data rate) "
180 strmhz(buf1, sysinfo.freqDDRBus/2),
181 strmhz(buf2, sysinfo.freqDDRBus));
186 #if defined(CONFIG_FSL_LBC)
187 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
188 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
190 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
191 sysinfo.freqLocalBus);
195 #if defined(CONFIG_FSL_IFC)
196 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
200 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
204 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
207 #ifdef CONFIG_SYS_DPAA_FMAN
208 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
209 printf(" FMAN%d: %s MHz\n", i + 1,
210 strmhz(buf1, sysinfo.freqFMan[i]));
214 #ifdef CONFIG_SYS_DPAA_PME
215 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
218 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
224 /* ------------------------------------------------------------------------- */
226 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
228 /* Everything after the first generation of PQ3 parts has RSTCR */
229 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
230 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
231 unsigned long val, msr;
234 * Initiate hard reset in debug control register DBCR0
235 * Make sure MSR[DE] = 1. This only resets the core.
245 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
247 /* Attempt board-specific reset */
250 /* Next try asserting HRESET_REQ */
251 out_be32(&gur->rstcr, 0x2);
260 * Get timebase clock frequency
262 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
263 #define CONFIG_SYS_FSL_TBCLK_DIV 8
265 unsigned long get_tbclk (void)
267 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
269 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
273 #if defined(CONFIG_WATCHDOG)
277 int re_enable = disable_interrupts();
278 reset_85xx_watchdog();
279 if (re_enable) enable_interrupts();
283 reset_85xx_watchdog(void)
286 * Clear TSR(WIS) bit by writing 1
288 mtspr(SPRN_TSR, TSR_WIS);
290 #endif /* CONFIG_WATCHDOG */
293 * Initializes on-chip MMC controllers.
294 * to override, implement board_mmc_init()
296 int cpu_mmc_init(bd_t *bis)
298 #ifdef CONFIG_FSL_ESDHC
299 return fsl_esdhc_mmc_init(bis);
306 * Print out the state of various machine registers.
307 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
308 * parameters for IFC and TLBs
310 void mpc85xx_reginfo(void)
314 #if defined(CONFIG_FSL_LBC)
317 #ifdef CONFIG_FSL_IFC
323 /* Common ddr init for non-corenet fsl 85xx platforms */
324 #ifndef CONFIG_FSL_CORENET
325 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
326 phys_size_t initdram(int board_type)
328 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
329 return fsl_ddr_sdram_size();
331 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
334 #else /* CONFIG_SYS_RAMBOOT */
335 phys_size_t initdram(int board_type)
337 phys_size_t dram_size = 0;
339 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
341 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
346 * Work around to stabilize DDR DLL
348 out_be32(&gur->ddrdllcr, 0x81000000);
349 asm("sync;isync;msync");
351 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
352 setbits_be32(&gur->devdisr, 0x00010000);
353 for (i = 0; i < x; i++)
355 clrbits_be32(&gur->devdisr, 0x00010000);
361 #if defined(CONFIG_SPD_EEPROM) || \
362 defined(CONFIG_DDR_SPD) || \
363 defined(CONFIG_SYS_DDR_RAW_TIMING)
364 dram_size = fsl_ddr_sdram();
366 dram_size = fixed_sdram();
368 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
369 dram_size *= 0x100000;
371 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
373 * Initialize and enable DDR ECC.
375 ddr_enable_ecc(dram_size);
378 #if defined(CONFIG_FSL_LBC)
379 /* Some boards also have sdram on the lbc */
386 #endif /* CONFIG_SYS_RAMBOOT */
389 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
391 /* Board-specific functions defined in each board's ddr.c */
392 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
393 unsigned int ctrl_num);
394 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
397 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
399 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
401 static void dump_spd_ddr_reg(void)
406 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
408 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
410 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
411 fsl_ddr_get_spd(spd[i], i);
413 puts("SPD data of all dimms (zero vaule is omitted)...\n");
416 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
417 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
418 printf("Dimm%d ", k++);
421 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
423 printf("%3d (0x%02x) ", k, k);
424 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
425 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
426 p_8 = (u8 *) &spd[i][j];
428 printf("0x%02x ", p_8[k]);
440 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
443 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
445 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
447 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
450 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
452 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
455 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
457 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
461 printf("%s unexpected controller number = %u\n",
466 printf("DDR registers dump for all controllers "
467 "(zero vaule is omitted)...\n");
468 puts("Offset (hex) ");
469 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
470 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
472 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
474 printf("%6d (0x%04x)", k * 4, k * 4);
475 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
476 p_32 = (u32 *) ddr[i];
478 printf(" 0x%08x", p_32[k]);
491 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
492 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
494 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
496 u32 tsize, valid, ptr;
499 clear_ddr_tlbs_phys(p_addr, size>>20);
501 /* Setup new tlb to cover the physical address */
502 setup_ddr_tlbs_phys(p_addr, size>>20);
505 ddr_esel = find_tlb_idx((void *)ptr, 1);
506 if (ddr_esel != -1) {
507 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
509 printf("TLB error in function %s\n", __func__);
517 * slide the testing window up to test another area
518 * for 32_bit system, the maximum testable memory is limited to
519 * CONFIG_MAX_MEM_MAPPED
521 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
523 phys_addr_t test_cap, p_addr;
524 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
526 #if !defined(CONFIG_PHYS_64BIT) || \
527 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
528 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
531 test_cap = gd->ram_size;
533 p_addr = (*vstart) + (*size) + (*phys_offset);
534 if (p_addr < test_cap - 1) {
535 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
536 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
538 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
539 *size = (u32) p_size;
540 printf("Testing 0x%08llx - 0x%08llx\n",
541 (u64)(*vstart) + (*phys_offset),
542 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
549 /* initialization for testing area */
550 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
552 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
554 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
555 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
558 #if !defined(CONFIG_PHYS_64BIT) || \
559 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
560 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
561 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
562 puts("Cannot test more than ");
563 print_size(CONFIG_MAX_MEM_MAPPED,
564 " without proper 36BIT support.\n");
567 printf("Testing 0x%08llx - 0x%08llx\n",
568 (u64)(*vstart) + (*phys_offset),
569 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
574 /* invalid TLBs for DDR and remap as normal after testing */
575 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
578 u32 tsize, valid, ptr;
582 /* disable the TLBs for this testing */
585 while (ptr < (*vstart) + (*size)) {
586 ddr_esel = find_tlb_idx((void *)ptr, 1);
587 if (ddr_esel != -1) {
588 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
589 disable_tlb(ddr_esel);
591 ptr += TSIZE_TO_BYTES(tsize);
595 setup_ddr_tlbs(gd->ram_size>>20);
601 void arch_memory_failure_handle(void)