git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc85xx/cpu_init.c

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <watchdog.h>
  15 #include <asm/processor.h>
  16 #include <ioports.h>
  17 #include <sata.h>
  18 #include <fm_eth.h>
  19 #include <asm/io.h>
  20 #include <asm/cache.h>
  21 #include <asm/mmu.h>
  22 #include <fsl_errata.h>
  23 #include <asm/fsl_law.h>
  24 #include <asm/fsl_serdes.h>
  25 #include <asm/fsl_srio.h>
  26 #ifdef CONFIG_FSL_CORENET
  27 #include <asm/fsl_portals.h>
  28 #include <asm/fsl_liodn.h>
  29 #endif
  30 #include <fsl_usb.h>
  31 #include <hwconfig.h>
  32 #include <linux/compiler.h>
  33 #include "mp.h"
  34 #ifdef CONFIG_CHAIN_OF_TRUST
  35 #include <fsl_validate.h>
  36 #endif
  37 #ifdef CONFIG_FSL_CAAM
  38 #include <fsl_sec.h>
  39 #endif
  40 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
  41 #include <nand.h>
  42 #include <errno.h>
  43 #endif
  44
  45 #include "../../../../drivers/block/fsl_sata.h"
  46 #ifdef CONFIG_U_QE
  47 #include "../../../../drivers/qe/qe.h"
  48 #endif
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  53 /*
  54  * For deriving usb clock from 100MHz sysclk, reference divisor is set
  55  * to a value of 5, which gives an intermediate value 20(100/5). The
  56  * multiplication factor integer is set to 24, which when multiplied to
  57  * above intermediate value provides clock for usb ip.
  58  */
  59 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
  60 {
  61         sys_info_t sysinfo;
  62
  63         get_sys_info(&sysinfo);
  64         if (sysinfo.diff_sysclk == 1) {
  65                 clrbits_be32(&usb_phy->pllprg[1],
  66                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
  67                 setbits_be32(&usb_phy->pllprg[1],
  68                              CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
  69                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
  70                              CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
  71                 }
  72 }
  73 #endif
  74
  75 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  76 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
  77 {
  78 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  79         u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
  80
  81         /* Increase Disconnect Threshold by 50mV */
  82         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  83                                                 INC_DCNT_THRESHOLD_50MV;
  84         /* Enable programming of USB High speed Disconnect threshold */
  85         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  86         out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
  87
  88         xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
  89         /* Increase Disconnect Threshold by 50mV */
  90         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  91                                                 INC_DCNT_THRESHOLD_50MV;
  92         /* Enable programming of USB High speed Disconnect threshold */
  93         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  94         out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
  95 #else
  96
  97         u32 temp = 0;
  98         u32 status = in_be32(&usb_phy->status1);
  99
 100         u32 squelch_prog_rd_0_2 =
 101                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
 102                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
 103
 104         u32 squelch_prog_rd_3_5 =
 105                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
 106                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
 107
 108         setbits_be32(&usb_phy->config1,
 109                      CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
 110         setbits_be32(&usb_phy->config2,
 111                      CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
 112
 113         temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
 114         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 115
 116         temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
 117         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 118 #endif
 119 }
 120 #endif
 121
 122
 123 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
 124 extern qe_iop_conf_t qe_iop_conf_tab[];
 125 extern void qe_config_iopin(u8 port, u8 pin, int dir,
 126                                 int open_drain, int assign);
 127 extern void qe_init(uint qe_base);
 128 extern void qe_reset(void);
 129
 130 static void config_qe_ioports(void)
 131 {
 132         u8      port, pin;
 133         int     dir, open_drain, assign;
 134         int     i;
 135
 136         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
 137                 port            = qe_iop_conf_tab[i].port;
 138                 pin             = qe_iop_conf_tab[i].pin;
 139                 dir             = qe_iop_conf_tab[i].dir;
 140                 open_drain      = qe_iop_conf_tab[i].open_drain;
 141                 assign          = qe_iop_conf_tab[i].assign;
 142                 qe_config_iopin(port, pin, dir, open_drain, assign);
 143         }
 144 }
 145 #endif
 146
 147 #ifdef CONFIG_CPM2
 148 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 149 {
 150         int portnum;
 151
 152         for (portnum = 0; portnum < 4; portnum++) {
 153                 uint pmsk = 0,
 154                      ppar = 0,
 155                      psor = 0,
 156                      pdir = 0,
 157                      podr = 0,
 158                      pdat = 0;
 159                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
 160                 iop_conf_t *eiopc = iopc + 32;
 161                 uint msk = 1;
 162
 163                 /*
 164                  * NOTE:
 165                  * index 0 refers to pin 31,
 166                  * index 31 refers to pin 0
 167                  */
 168                 while (iopc < eiopc) {
 169                         if (iopc->conf) {
 170                                 pmsk |= msk;
 171                                 if (iopc->ppar)
 172                                         ppar |= msk;
 173                                 if (iopc->psor)
 174                                         psor |= msk;
 175                                 if (iopc->pdir)
 176                                         pdir |= msk;
 177                                 if (iopc->podr)
 178                                         podr |= msk;
 179                                 if (iopc->pdat)
 180                                         pdat |= msk;
 181                         }
 182
 183                         msk <<= 1;
 184                         iopc++;
 185                 }
 186
 187                 if (pmsk != 0) {
 188                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
 189                         uint tpmsk = ~pmsk;
 190
 191                         /*
 192                          * the (somewhat confused) paragraph at the
 193                          * bottom of page 35-5 warns that there might
 194                          * be "unknown behaviour" when programming
 195                          * PSORx and PDIRx, if PPARx = 1, so I
 196                          * decided this meant I had to disable the
 197                          * dedicated function first, and enable it
 198                          * last.
 199                          */
 200                         iop->ppar &= tpmsk;
 201                         iop->psor = (iop->psor & tpmsk) | psor;
 202                         iop->podr = (iop->podr & tpmsk) | podr;
 203                         iop->pdat = (iop->pdat & tpmsk) | pdat;
 204                         iop->pdir = (iop->pdir & tpmsk) | pdir;
 205                         iop->ppar |= ppar;
 206                 }
 207         }
 208 }
 209 #endif
 210
 211 #ifdef CONFIG_SYS_FSL_CPC
 212 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
 213 void disable_cpc_sram(void)
 214 {
 215         int i;
 216
 217         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 218
 219         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 220                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 221                         /* find and disable LAW of SRAM */
 222                         struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
 223
 224                         if (law.index == -1) {
 225                                 printf("\nFatal error happened\n");
 226                                 return;
 227                         }
 228                         disable_law(law.index);
 229
 230                         clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
 231                         out_be32(&cpc->cpccsr0, 0);
 232                         out_be32(&cpc->cpcsrcr0, 0);
 233                 }
 234         }
 235 }
 236 #endif
 237
 238 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 239 #ifdef CONFIG_POST
 240 #error POST memory test cannot be enabled with TDM
 241 #endif
 242 static void enable_tdm_law(void)
 243 {
 244         int ret;
 245         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
 246         int tdm_hwconfig_enabled = 0;
 247
 248         /*
 249          * Extract hwconfig from environment since environment
 250          * is not setup properly yet. Search for tdm entry in
 251          * hwconfig.
 252          */
 253         ret = getenv_f("hwconfig", buffer, sizeof(buffer));
 254         if (ret > 0) {
 255                 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
 256                 /* If tdm is defined in hwconfig, set law for tdm workaround */
 257                 if (tdm_hwconfig_enabled)
 258                         set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
 259                                      LAW_TRGT_IF_CCSR);
 260         }
 261 }
 262 #endif
 263
 264 void enable_cpc(void)
 265 {
 266         int i;
 267         int ret;
 268         u32 size = 0;
 269         u32 cpccfg0;
 270         char buffer[HWCONFIG_BUFFER_SIZE];
 271         char cpc_subarg[16];
 272         bool have_hwconfig = false;
 273         int cpc_args = 0;
 274         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 275
 276         /* Extract hwconfig from environment */
 277         ret = getenv_f("hwconfig", buffer, sizeof(buffer));
 278         if (ret > 0) {
 279                 /*
 280                  * If "en_cpc" is not defined in hwconfig then by default all
 281                  * cpcs are enable. If this config is defined then individual
 282                  * cpcs which have to be enabled should also be defined.
 283                  * e.g en_cpc:cpc1,cpc2;
 284                  */
 285                 if (hwconfig_f("en_cpc", buffer))
 286                         have_hwconfig = true;
 287         }
 288
 289         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 290                 if (have_hwconfig) {
 291                         sprintf(cpc_subarg, "cpc%u", i + 1);
 292                         cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
 293                         if (cpc_args == 0)
 294                                 continue;
 295                 }
 296                 cpccfg0 = in_be32(&cpc->cpccfg0);
 297                 size += CPC_CFG0_SZ_K(cpccfg0);
 298
 299 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 300                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 301 #endif
 302 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
 303                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 304 #endif
 305 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 306                 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
 307 #endif
 308 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
 309                 if (has_erratum_a006379()) {
 310                         setbits_be32(&cpc->cpchdbcr0,
 311                                      CPC_HDBCR0_SPLRU_LEVEL_EN);
 312                 }
 313 #endif
 314
 315                 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 316                 /* Read back to sync write */
 317                 in_be32(&cpc->cpccsr0);
 318
 319         }
 320
 321         puts("Corenet Platform Cache: ");
 322         print_size(size * 1024, " enabled\n");
 323 }
 324
 325 static void invalidate_cpc(void)
 326 {
 327         int i;
 328         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 329
 330         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 331                 /* skip CPC when it used as all SRAM */
 332                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
 333                         continue;
 334                 /* Flash invalidate the CPC and clear all the locks */
 335                 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
 336                 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
 337                         ;
 338         }
 339 }
 340 #else
 341 #define enable_cpc()
 342 #define invalidate_cpc()
 343 #define disable_cpc_sram()
 344 #endif /* CONFIG_SYS_FSL_CPC */
 345
 346 /*
 347  * Breathe some life into the CPU...
 348  *
 349  * Set up the memory map
 350  * initialize a bunch of registers
 351  */
 352
 353 #ifdef CONFIG_FSL_CORENET
 354 static void corenet_tb_init(void)
 355 {
 356         volatile ccsr_rcpm_t *rcpm =
 357                 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 358         volatile ccsr_pic_t *pic =
 359                 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 360         u32 whoami = in_be32(&pic->whoami);
 361
 362         /* Enable the timebase register for this core */
 363         out_be32(&rcpm->ctbenrl, (1 << whoami));
 364 }
 365 #endif
 366
 367 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 368 void fsl_erratum_a007212_workaround(void)
 369 {
 370         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 371         u32 ddr_pll_ratio;
 372         u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
 373         u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
 374         u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
 375 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 376         u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
 377         u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
 378 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
 379         u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
 380         u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
 381 #endif
 382 #endif
 383         /*
 384          * Even this workaround applies to selected version of SoCs, it is
 385          * safe to apply to all versions, with the limitation of odd ratios.
 386          * If RCW has disabled DDR PLL, we have to apply this workaround,
 387          * otherwise DDR will not work.
 388          */
 389         ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
 390                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
 391                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 392         /* check if RCW sets ratio to 0, required by this workaround */
 393         if (ddr_pll_ratio != 0)
 394                 return;
 395         ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
 396                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
 397                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 398         /* check if reserved bits have the desired ratio */
 399         if (ddr_pll_ratio == 0) {
 400                 printf("Error: Unknown DDR PLL ratio!\n");
 401                 return;
 402         }
 403         ddr_pll_ratio >>= 1;
 404
 405         setbits_be32(plldadcr1, 0x02000001);
 406 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 407         setbits_be32(plldadcr2, 0x02000001);
 408 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
 409         setbits_be32(plldadcr3, 0x02000001);
 410 #endif
 411 #endif
 412         setbits_be32(dpdovrcr4, 0xe0000000);
 413         out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
 414 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 415         out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
 416 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
 417         out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
 418 #endif
 419 #endif
 420         udelay(100);
 421         clrbits_be32(plldadcr1, 0x02000001);
 422 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 423         clrbits_be32(plldadcr2, 0x02000001);
 424 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
 425         clrbits_be32(plldadcr3, 0x02000001);
 426 #endif
 427 #endif
 428         clrbits_be32(dpdovrcr4, 0xe0000000);
 429 }
 430 #endif
 431
 432 ulong cpu_init_f(void)
 433 {
 434         extern void m8560_cpm_reset (void);
 435 #if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
 436         (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
 437         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 438 #endif
 439 #if defined(CONFIG_SECURE_BOOT)
 440         struct law_entry law;
 441 #endif
 442 #ifdef CONFIG_MPC8548
 443         ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 444         uint svr = get_svr();
 445
 446         /*
 447          * CPU2 errata workaround: A core hang possible while executing
 448          * a msync instruction and a snoopable transaction from an I/O
 449          * master tagged to make quick forward progress is present.
 450          * Fixed in silicon rev 2.1.
 451          */
 452         if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 453                 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 454 #endif
 455
 456         disable_tlb(14);
 457         disable_tlb(15);
 458
 459 #if defined(CONFIG_SECURE_BOOT)
 460         /* Disable the LAW created for NOR flash by the PBI commands */
 461         law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 462         if (law.index != -1)
 463                 disable_law(law.index);
 464
 465 #if defined(CONFIG_SYS_CPC_REINIT_F)
 466         disable_cpc_sram();
 467 #endif
 468
 469 #if defined(CONFIG_FSL_CORENET)
 470         /* Put PAMU in bypass mode */
 471         out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
 472 #endif
 473
 474 #endif
 475
 476 #ifdef CONFIG_CPM2
 477         config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 478 #endif
 479
 480        init_early_memctl_regs();
 481
 482 #if defined(CONFIG_CPM2)
 483         m8560_cpm_reset();
 484 #endif
 485
 486 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
 487         /* Config QE ioports */
 488         config_qe_ioports();
 489 #endif
 490
 491 #if defined(CONFIG_FSL_DMA)
 492         dma_init();
 493 #endif
 494 #ifdef CONFIG_FSL_CORENET
 495         corenet_tb_init();
 496 #endif
 497         init_used_tlb_cams();
 498
 499         /* Invalidate the CPC before DDR gets enabled */
 500         invalidate_cpc();
 501
 502  #ifdef CONFIG_SYS_DCSRBAR_PHYS
 503         /* set DCSRCR so that DCSR space is 1G */
 504         setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
 505         in_be32(&gur->dcsrcr);
 506 #endif
 507
 508 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 509         fsl_erratum_a007212_workaround();
 510 #endif
 511
 512         return 0;
 513 }
 514
 515 /* Implement a dummy function for those platforms w/o SERDES */
 516 static void __fsl_serdes__init(void)
 517 {
 518         return ;
 519 }
 520 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 521
 522 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 523 int enable_cluster_l2(void)
 524 {
 525         int i = 0;
 526         u32 cluster, svr = get_svr();
 527         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 528         struct ccsr_cluster_l2 __iomem *l2cache;
 529
 530         /* only the L2 of first cluster should be enabled as expected on T4080,
 531          * but there is no EOC in the first cluster as HW sake, so return here
 532          * to skip enabling L2 cache of the 2nd cluster.
 533          */
 534         if (SVR_SOC_VER(svr) == SVR_T4080)
 535                 return 0;
 536
 537         cluster = in_be32(&gur->tp_cluster[i].lower);
 538         if (cluster & TP_CLUSTER_EOC)
 539                 return 0;
 540
 541         /* The first cache has already been set up, so skip it */
 542         i++;
 543
 544         /* Look through the remaining clusters, and set up their caches */
 545         do {
 546                 int j, cluster_valid = 0;
 547
 548                 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
 549
 550                 cluster = in_be32(&gur->tp_cluster[i].lower);
 551
 552                 /* check that at least one core/accel is enabled in cluster */
 553                 for (j = 0; j < 4; j++) {
 554                         u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
 555                         u32 type = in_be32(&gur->tp_ityp[idx]);
 556
 557                         if ((type & TP_ITYP_AV) &&
 558                             TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
 559                                 cluster_valid = 1;
 560                 }
 561
 562                 if (cluster_valid) {
 563                         /* set stash ID to (cluster) * 2 + 32 + 1 */
 564                         clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
 565
 566                         printf("enable l2 for cluster %d %p\n", i, l2cache);
 567
 568                         out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
 569                         while ((in_be32(&l2cache->l2csr0)
 570                                 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
 571                                         ;
 572                         out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
 573                 }
 574                 i++;
 575         } while (!(cluster & TP_CLUSTER_EOC));
 576
 577         return 0;
 578 }
 579 #endif
 580
 581 /*
 582  * Initialize L2 as cache.
 583  */
 584 int l2cache_init(void)
 585 {
 586         __maybe_unused u32 svr = get_svr();
 587 #ifdef CONFIG_L2_CACHE
 588         ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
 589 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 590         struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 591 #endif
 592
 593         puts ("L2:    ");
 594
 595 #if defined(CONFIG_L2_CACHE)
 596         volatile uint cache_ctl;
 597         uint ver;
 598         u32 l2siz_field;
 599
 600         ver = SVR_SOC_VER(svr);
 601
 602         asm("msync;isync");
 603         cache_ctl = l2cache->l2ctl;
 604
 605 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 606         if (cache_ctl & MPC85xx_L2CTL_L2E) {
 607                 /* Clear L2 SRAM memory-mapped base address */
 608                 out_be32(&l2cache->l2srbar0, 0x0);
 609                 out_be32(&l2cache->l2srbar1, 0x0);
 610
 611                 /* set MBECCDIS=0, SBECCDIS=0 */
 612                 clrbits_be32(&l2cache->l2errdis,
 613                                 (MPC85xx_L2ERRDIS_MBECC |
 614                                  MPC85xx_L2ERRDIS_SBECC));
 615
 616                 /* set L2E=0, L2SRAM=0 */
 617                 clrbits_be32(&l2cache->l2ctl,
 618                                 (MPC85xx_L2CTL_L2E |
 619                                  MPC85xx_L2CTL_L2SRAM_ENTIRE));
 620         }
 621 #endif
 622
 623         l2siz_field = (cache_ctl >> 28) & 0x3;
 624
 625         switch (l2siz_field) {
 626         case 0x0:
 627                 printf(" unknown size (0x%08x)\n", cache_ctl);
 628                 return -1;
 629                 break;
 630         case 0x1:
 631                 if (ver == SVR_8540 || ver == SVR_8560   ||
 632                     ver == SVR_8541 || ver == SVR_8555) {
 633                         puts("128 KiB ");
 634                         /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
 635                         cache_ctl = 0xc4000000;
 636                 } else {
 637                         puts("256 KiB ");
 638                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 639                 }
 640                 break;
 641         case 0x2:
 642                 if (ver == SVR_8540 || ver == SVR_8560   ||
 643                     ver == SVR_8541 || ver == SVR_8555) {
 644                         puts("256 KiB ");
 645                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
 646                         cache_ctl = 0xc8000000;
 647                 } else {
 648                         puts("512 KiB ");
 649                         /* set L2E=1, L2I=1, & L2SRAM=0 */
 650                         cache_ctl = 0xc0000000;
 651                 }
 652                 break;
 653         case 0x3:
 654                 puts("1024 KiB ");
 655                 /* set L2E=1, L2I=1, & L2SRAM=0 */
 656                 cache_ctl = 0xc0000000;
 657                 break;
 658         }
 659
 660         if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 661                 puts("already enabled");
 662 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
 663                 u32 l2srbar = l2cache->l2srbar0;
 664                 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 665                                 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
 666                         l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 667                         l2cache->l2srbar0 = l2srbar;
 668                         printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 669                 }
 670 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 671                 puts("\n");
 672         } else {
 673                 asm("msync;isync");
 674                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 675                 asm("msync;isync");
 676                 puts("enabled\n");
 677         }
 678 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 679         if (SVR_SOC_VER(svr) == SVR_P2040) {
 680                 puts("N/A\n");
 681                 goto skip_l2;
 682         }
 683
 684         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 685
 686         /* invalidate the L2 cache */
 687         mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
 688         while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 689                 ;
 690
 691 #ifdef CONFIG_SYS_CACHE_STASHING
 692         /* set stash id to (coreID) * 2 + 32 + L2 (1) */
 693         mtspr(SPRN_L2CSR1, (32 + 1));
 694 #endif
 695
 696         /* enable the cache */
 697         mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 698
 699         if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 700                 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 701                         ;
 702                 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
 703         }
 704
 705 skip_l2:
 706 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 707         if (l2cache->l2csr0 & L2CSR0_L2E)
 708                 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
 709                            " enabled\n");
 710
 711         enable_cluster_l2();
 712 #else
 713         puts("disabled\n");
 714 #endif
 715
 716         return 0;
 717 }
 718
 719 /*
 720  *
 721  * The newer 8548, etc, parts have twice as much cache, but
 722  * use the same bit-encoding as the older 8555, etc, parts.
 723  *
 724  */
 725 int cpu_init_r(void)
 726 {
 727         __maybe_unused u32 svr = get_svr();
 728 #ifdef CONFIG_SYS_LBC_LCRR
 729         fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
 730 #endif
 731 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 732         extern int spin_table_compat;
 733         const char *spin;
 734 #endif
 735 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 736         ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
 737 #endif
 738 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 739         defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 740         /*
 741          * CPU22 and NMG_CPU_A011 share the same workaround.
 742          * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 743          * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 744          * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
 745          * fixed in 2.0. NMG_CPU_A011 is activated by default and can
 746          * be disabled by hwconfig with syntax:
 747          *
 748          * fsl_cpu_a011:disable
 749          */
 750         extern int enable_cpu_a011_workaround;
 751 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
 752         enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
 753 #else
 754         char buffer[HWCONFIG_BUFFER_SIZE];
 755         char *buf = NULL;
 756         int n, res;
 757
 758         n = getenv_f("hwconfig", buffer, sizeof(buffer));
 759         if (n > 0)
 760                 buf = buffer;
 761
 762         res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
 763         if (res > 0) {
 764                 enable_cpu_a011_workaround = 0;
 765         } else {
 766                 if (n >= HWCONFIG_BUFFER_SIZE) {
 767                         printf("fsl_cpu_a011 was not found. hwconfig variable "
 768                                 "may be too long\n");
 769                 }
 770                 enable_cpu_a011_workaround =
 771                         (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
 772                         (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
 773         }
 774 #endif
 775         if (enable_cpu_a011_workaround) {
 776                 flush_dcache();
 777                 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 778                 sync();
 779         }
 780 #endif
 781 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
 782         /*
 783          * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
 784          * in write shadow mode. Checking DCWS before setting SPR 976.
 785          */
 786         if (mfspr(L1CSR2) & L1CSR2_DCWS)
 787                 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
 788 #endif
 789
 790 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 791         spin = getenv("spin_table_compat");
 792         if (spin && (*spin == 'n'))
 793                 spin_table_compat = 0;
 794         else
 795                 spin_table_compat = 1;
 796 #endif
 797
 798 #ifdef CONFIG_FSL_CORENET
 799         set_liodns();
 800 #ifdef CONFIG_SYS_DPAA_QBMAN
 801         setup_portals();
 802 #endif
 803 #endif
 804
 805         l2cache_init();
 806 #if defined(CONFIG_RAMBOOT_PBL)
 807         disable_cpc_sram();
 808 #endif
 809         enable_cpc();
 810 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 811         enable_tdm_law();
 812 #endif
 813
 814 #ifndef CONFIG_SYS_FSL_NO_SERDES
 815         /* needs to be in ram since code uses global static vars */
 816         fsl_serdes_init();
 817 #endif
 818
 819 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 820 #define MCFGR_AXIPIPE 0x000000f0
 821         if (IS_SVR_REV(svr, 1, 0))
 822                 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
 823 #endif
 824
 825 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
 826         if (IS_SVR_REV(svr, 1, 0)) {
 827                 int i;
 828                 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
 829
 830                 for (i = 0; i < 12; i++) {
 831                         p += i + (i > 5 ? 11 : 0);
 832                         out_be32(p, 0x2);
 833                 }
 834                 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
 835                 out_be32(p, 0x34);
 836         }
 837 #endif
 838
 839 #ifdef CONFIG_SYS_SRIO
 840         srio_init();
 841 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 842         char *s = getenv("bootmaster");
 843         if (s) {
 844                 if (!strcmp(s, "SRIO1")) {
 845                         srio_boot_master(1);
 846                         srio_boot_master_release_slave(1);
 847                 }
 848                 if (!strcmp(s, "SRIO2")) {
 849                         srio_boot_master(2);
 850                         srio_boot_master_release_slave(2);
 851                 }
 852         }
 853 #endif
 854 #endif
 855
 856 #if defined(CONFIG_MP)
 857         setup_mp();
 858 #endif
 859
 860 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
 861         {
 862                 if (SVR_MAJ(svr) < 3) {
 863                         void *p;
 864                         p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
 865                         setbits_be32(p, 1 << (31 - 14));
 866                 }
 867         }
 868 #endif
 869
 870 #ifdef CONFIG_SYS_LBC_LCRR
 871         /*
 872          * Modify the CLKDIV field of LCRR register to improve the writing
 873          * speed for NOR flash.
 874          */
 875         clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 876         __raw_readl(&lbc->lcrr);
 877         isync();
 878 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 879         udelay(100);
 880 #endif
 881 #endif
 882
 883 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 884         {
 885                 struct ccsr_usb_phy __iomem *usb_phy1 =
 886                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 887 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 888                 if (has_erratum_a006261())
 889                         fsl_erratum_a006261_workaround(usb_phy1);
 890 #endif
 891                 out_be32(&usb_phy1->usb_enable_override,
 892                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 893         }
 894 #endif
 895 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 896         {
 897                 struct ccsr_usb_phy __iomem *usb_phy2 =
 898                         (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
 899 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 900                 if (has_erratum_a006261())
 901                         fsl_erratum_a006261_workaround(usb_phy2);
 902 #endif
 903                 out_be32(&usb_phy2->usb_enable_override,
 904                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 905         }
 906 #endif
 907
 908 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
 909         /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
 910          * multi-bit ECC errors which has impact on performance, so software
 911          * should disable all ECC reporting from USB1 and USB2.
 912          */
 913         if (IS_SVR_REV(get_svr(), 1, 0)) {
 914                 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
 915                         (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
 916                 setbits_be32(&dcfg->ecccr1,
 917                                 (DCSR_DCFG_ECC_DISABLE_USB1 |
 918                                  DCSR_DCFG_ECC_DISABLE_USB2));
 919         }
 920 #endif
 921
 922 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
 923                 struct ccsr_usb_phy __iomem *usb_phy =
 924                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 925                 setbits_be32(&usb_phy->pllprg[1],
 926                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
 927                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
 928                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
 929                              CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
 930 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 931                 usb_single_source_clk_configure(usb_phy);
 932 #endif
 933                 setbits_be32(&usb_phy->port1.ctrl,
 934                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 935                 setbits_be32(&usb_phy->port1.drvvbuscfg,
 936                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 937                 setbits_be32(&usb_phy->port1.pwrfltcfg,
 938                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 939                 setbits_be32(&usb_phy->port2.ctrl,
 940                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 941                 setbits_be32(&usb_phy->port2.drvvbuscfg,
 942                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 943                 setbits_be32(&usb_phy->port2.pwrfltcfg,
 944                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 945
 946 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 947                 if (has_erratum_a006261())
 948                         fsl_erratum_a006261_workaround(usb_phy);
 949 #endif
 950
 951 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
 952
 953 #ifdef CONFIG_FMAN_ENET
 954         fman_enet_init();
 955 #endif
 956
 957 #ifdef CONFIG_FSL_CAAM
 958         sec_init();
 959 #endif
 960
 961 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
 962         /*
 963          * For P1022/1013 Rev1.0 silicon, after power on SATA host
 964          * controller is configured in legacy mode instead of the
 965          * expected enterprise mode. Software needs to clear bit[28]
 966          * of HControl register to change to enterprise mode from
 967          * legacy mode.  We assume that the controller is offline.
 968          */
 969         if (IS_SVR_REV(svr, 1, 0) &&
 970             ((SVR_SOC_VER(svr) == SVR_P1022) ||
 971              (SVR_SOC_VER(svr) == SVR_P1013))) {
 972                 fsl_sata_reg_t *reg;
 973
 974                 /* first SATA controller */
 975                 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
 976                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 977
 978                 /* second SATA controller */
 979                 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
 980                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 981         }
 982 #endif
 983
 984         init_used_tlb_cams();
 985
 986         return 0;
 987 }
 988
 989 void arch_preboot_os(void)
 990 {
 991         u32 msr;
 992
 993         /*
 994          * We are changing interrupt offsets and are about to boot the OS so
 995          * we need to make sure we disable all async interrupts. EE is already
 996          * disabled by the time we get called.
 997          */
 998         msr = mfmsr();
 999         msr &= ~(MSR_ME|MSR_CE);
1000         mtmsr(msr);
1001 }
1002
1003 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
1004 int sata_initialize(void)
1005 {
1006         if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
1007                 return __sata_initialize();
1008
1009         return 1;
1010 }
1011 #endif
1012
1013 void cpu_secondary_init_r(void)
1014 {
1015 #ifdef CONFIG_U_QE
1016         uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1017 #elif defined CONFIG_QE
1018         uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
1019 #endif
1020
1021 #ifdef CONFIG_QE
1022         qe_init(qe_base);
1023         qe_reset();
1024 #endif
1025 }
1026
1027 #ifdef CONFIG_BOARD_LATE_INIT
1028 int board_late_init(void)
1029 {
1030 #ifdef CONFIG_CHAIN_OF_TRUST
1031         fsl_setenv_chain_of_trust();
1032 #endif
1033
1034         return 0;
1035 }
1036 #endif