2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/processor.h>
20 #include <asm/cache.h>
22 #include <asm/fsl_errata.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h>
28 #include <linux/compiler.h>
30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
35 #include "../../../../drivers/block/fsl_sata.h"
37 #include "../../../../drivers/qe/qe.h"
40 DECLARE_GLOBAL_DATA_PTR;
42 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
43 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
45 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
46 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
48 /* Increase Disconnect Threshold by 50mV */
49 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
50 INC_DCNT_THRESHOLD_50MV;
51 /* Enable programming of USB High speed Disconnect threshold */
52 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
53 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
55 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
56 /* Increase Disconnect Threshold by 50mV */
57 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
58 INC_DCNT_THRESHOLD_50MV;
59 /* Enable programming of USB High speed Disconnect threshold */
60 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
61 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
65 u32 status = in_be32(&usb_phy->status1);
67 u32 squelch_prog_rd_0_2 =
68 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
69 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
71 u32 squelch_prog_rd_3_5 =
72 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
73 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
75 setbits_be32(&usb_phy->config1,
76 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
77 setbits_be32(&usb_phy->config2,
78 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
80 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
81 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
83 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
84 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
90 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
91 extern qe_iop_conf_t qe_iop_conf_tab[];
92 extern void qe_config_iopin(u8 port, u8 pin, int dir,
93 int open_drain, int assign);
94 extern void qe_init(uint qe_base);
95 extern void qe_reset(void);
97 static void config_qe_ioports(void)
100 int dir, open_drain, assign;
103 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
104 port = qe_iop_conf_tab[i].port;
105 pin = qe_iop_conf_tab[i].pin;
106 dir = qe_iop_conf_tab[i].dir;
107 open_drain = qe_iop_conf_tab[i].open_drain;
108 assign = qe_iop_conf_tab[i].assign;
109 qe_config_iopin(port, pin, dir, open_drain, assign);
115 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
119 for (portnum = 0; portnum < 4; portnum++) {
126 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
127 iop_conf_t *eiopc = iopc + 32;
132 * index 0 refers to pin 31,
133 * index 31 refers to pin 0
135 while (iopc < eiopc) {
155 volatile ioport_t *iop = ioport_addr (cpm, portnum);
159 * the (somewhat confused) paragraph at the
160 * bottom of page 35-5 warns that there might
161 * be "unknown behaviour" when programming
162 * PSORx and PDIRx, if PPARx = 1, so I
163 * decided this meant I had to disable the
164 * dedicated function first, and enable it
168 iop->psor = (iop->psor & tpmsk) | psor;
169 iop->podr = (iop->podr & tpmsk) | podr;
170 iop->pdat = (iop->pdat & tpmsk) | pdat;
171 iop->pdir = (iop->pdir & tpmsk) | pdir;
178 #ifdef CONFIG_SYS_FSL_CPC
179 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
180 static void disable_cpc_sram(void)
184 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
186 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
187 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
188 /* find and disable LAW of SRAM */
189 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
191 if (law.index == -1) {
192 printf("\nFatal error happened\n");
195 disable_law(law.index);
197 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
198 out_be32(&cpc->cpccsr0, 0);
199 out_be32(&cpc->cpcsrcr0, 0);
205 static void enable_cpc(void)
210 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
212 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
213 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
214 size += CPC_CFG0_SZ_K(cpccfg0);
216 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
217 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
219 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
220 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
222 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
223 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
225 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
226 if (has_erratum_a006379()) {
227 setbits_be32(&cpc->cpchdbcr0,
228 CPC_HDBCR0_SPLRU_LEVEL_EN);
232 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
233 /* Read back to sync write */
234 in_be32(&cpc->cpccsr0);
238 puts("Corenet Platform Cache: ");
239 print_size(size * 1024, " enabled\n");
242 static void invalidate_cpc(void)
245 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
247 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
248 /* skip CPC when it used as all SRAM */
249 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
251 /* Flash invalidate the CPC and clear all the locks */
252 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
253 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
259 #define invalidate_cpc()
260 #endif /* CONFIG_SYS_FSL_CPC */
263 * Breathe some life into the CPU...
265 * Set up the memory map
266 * initialize a bunch of registers
269 #ifdef CONFIG_FSL_CORENET
270 static void corenet_tb_init(void)
272 volatile ccsr_rcpm_t *rcpm =
273 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
274 volatile ccsr_pic_t *pic =
275 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
276 u32 whoami = in_be32(&pic->whoami);
278 /* Enable the timebase register for this core */
279 out_be32(&rcpm->ctbenrl, (1 << whoami));
283 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
284 void fsl_erratum_a007212_workaround(void)
286 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
288 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
289 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
290 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
291 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
292 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
293 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
294 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
295 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
296 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
300 * Even this workaround applies to selected version of SoCs, it is
301 * safe to apply to all versions, with the limitation of odd ratios.
302 * If RCW has disabled DDR PLL, we have to apply this workaround,
303 * otherwise DDR will not work.
305 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
306 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
307 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
308 /* check if RCW sets ratio to 0, required by this workaround */
309 if (ddr_pll_ratio != 0)
311 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
312 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
313 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
314 /* check if reserved bits have the desired ratio */
315 if (ddr_pll_ratio == 0) {
316 printf("Error: Unknown DDR PLL ratio!\n");
321 setbits_be32(plldadcr1, 0x02000001);
322 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
323 setbits_be32(plldadcr2, 0x02000001);
324 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
325 setbits_be32(plldadcr3, 0x02000001);
328 setbits_be32(dpdovrcr4, 0xe0000000);
329 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
330 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
331 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
332 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
333 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
337 clrbits_be32(plldadcr1, 0x02000001);
338 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
339 clrbits_be32(plldadcr2, 0x02000001);
340 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
341 clrbits_be32(plldadcr3, 0x02000001);
344 clrbits_be32(dpdovrcr4, 0xe0000000);
348 void cpu_init_f (void)
350 extern void m8560_cpm_reset (void);
351 #ifdef CONFIG_SYS_DCSRBAR_PHYS
352 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
354 #if defined(CONFIG_SECURE_BOOT)
355 struct law_entry law;
357 #ifdef CONFIG_MPC8548
358 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
359 uint svr = get_svr();
362 * CPU2 errata workaround: A core hang possible while executing
363 * a msync instruction and a snoopable transaction from an I/O
364 * master tagged to make quick forward progress is present.
365 * Fixed in silicon rev 2.1.
367 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
368 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
374 #if defined(CONFIG_SECURE_BOOT)
375 /* Disable the LAW created for NOR flash by the PBI commands */
376 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
378 disable_law(law.index);
380 #if defined(CONFIG_SYS_CPC_REINIT_F)
386 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
389 init_early_memctl_regs();
391 #if defined(CONFIG_CPM2)
395 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
396 /* Config QE ioports */
400 #if defined(CONFIG_FSL_DMA)
403 #ifdef CONFIG_FSL_CORENET
406 init_used_tlb_cams();
408 /* Invalidate the CPC before DDR gets enabled */
411 #ifdef CONFIG_SYS_DCSRBAR_PHYS
412 /* set DCSRCR so that DCSR space is 1G */
413 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
414 in_be32(&gur->dcsrcr);
417 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
418 fsl_erratum_a007212_workaround();
423 /* Implement a dummy function for those platforms w/o SERDES */
424 static void __fsl_serdes__init(void)
428 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
430 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
431 int enable_cluster_l2(void)
435 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
436 struct ccsr_cluster_l2 __iomem *l2cache;
438 cluster = in_be32(&gur->tp_cluster[i].lower);
439 if (cluster & TP_CLUSTER_EOC)
442 /* The first cache has already been set up, so skip it */
445 /* Look through the remaining clusters, and set up their caches */
447 int j, cluster_valid = 0;
449 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
451 cluster = in_be32(&gur->tp_cluster[i].lower);
453 /* check that at least one core/accel is enabled in cluster */
454 for (j = 0; j < 4; j++) {
455 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
456 u32 type = in_be32(&gur->tp_ityp[idx]);
458 if (type & TP_ITYP_AV)
463 /* set stash ID to (cluster) * 2 + 32 + 1 */
464 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
466 printf("enable l2 for cluster %d %p\n", i, l2cache);
468 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
469 while ((in_be32(&l2cache->l2csr0)
470 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
472 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
475 } while (!(cluster & TP_CLUSTER_EOC));
482 * Initialize L2 as cache.
484 * The newer 8548, etc, parts have twice as much cache, but
485 * use the same bit-encoding as the older 8555, etc, parts.
490 __maybe_unused u32 svr = get_svr();
491 #ifdef CONFIG_SYS_LBC_LCRR
492 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
494 #ifdef CONFIG_L2_CACHE
495 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
496 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
497 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
499 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
500 extern int spin_table_compat;
503 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
504 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
506 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
507 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
509 * CPU22 and NMG_CPU_A011 share the same workaround.
510 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
511 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
512 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
513 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
514 * be disabled by hwconfig with syntax:
516 * fsl_cpu_a011:disable
518 extern int enable_cpu_a011_workaround;
519 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
520 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
522 char buffer[HWCONFIG_BUFFER_SIZE];
526 n = getenv_f("hwconfig", buffer, sizeof(buffer));
530 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
532 enable_cpu_a011_workaround = 0;
534 if (n >= HWCONFIG_BUFFER_SIZE) {
535 printf("fsl_cpu_a011 was not found. hwconfig variable "
536 "may be too long\n");
538 enable_cpu_a011_workaround =
539 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
540 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
543 if (enable_cpu_a011_workaround) {
545 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
549 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
551 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
552 * in write shadow mode. Checking DCWS before setting SPR 976.
554 if (mfspr(L1CSR2) & L1CSR2_DCWS)
555 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
558 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
559 spin = getenv("spin_table_compat");
560 if (spin && (*spin == 'n'))
561 spin_table_compat = 0;
563 spin_table_compat = 1;
568 #if defined(CONFIG_L2_CACHE)
569 volatile uint cache_ctl;
573 ver = SVR_SOC_VER(svr);
576 cache_ctl = l2cache->l2ctl;
578 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
579 if (cache_ctl & MPC85xx_L2CTL_L2E) {
580 /* Clear L2 SRAM memory-mapped base address */
581 out_be32(&l2cache->l2srbar0, 0x0);
582 out_be32(&l2cache->l2srbar1, 0x0);
584 /* set MBECCDIS=0, SBECCDIS=0 */
585 clrbits_be32(&l2cache->l2errdis,
586 (MPC85xx_L2ERRDIS_MBECC |
587 MPC85xx_L2ERRDIS_SBECC));
589 /* set L2E=0, L2SRAM=0 */
590 clrbits_be32(&l2cache->l2ctl,
592 MPC85xx_L2CTL_L2SRAM_ENTIRE));
596 l2siz_field = (cache_ctl >> 28) & 0x3;
598 switch (l2siz_field) {
600 printf(" unknown size (0x%08x)\n", cache_ctl);
604 if (ver == SVR_8540 || ver == SVR_8560 ||
605 ver == SVR_8541 || ver == SVR_8555) {
607 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
608 cache_ctl = 0xc4000000;
611 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
615 if (ver == SVR_8540 || ver == SVR_8560 ||
616 ver == SVR_8541 || ver == SVR_8555) {
618 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
619 cache_ctl = 0xc8000000;
622 /* set L2E=1, L2I=1, & L2SRAM=0 */
623 cache_ctl = 0xc0000000;
628 /* set L2E=1, L2I=1, & L2SRAM=0 */
629 cache_ctl = 0xc0000000;
633 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
634 puts("already enabled");
635 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
636 u32 l2srbar = l2cache->l2srbar0;
637 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
638 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
639 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
640 l2cache->l2srbar0 = l2srbar;
641 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
643 #endif /* CONFIG_SYS_INIT_L2_ADDR */
647 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
651 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
652 if (SVR_SOC_VER(svr) == SVR_P2040) {
657 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
659 /* invalidate the L2 cache */
660 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
661 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
664 #ifdef CONFIG_SYS_CACHE_STASHING
665 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
666 mtspr(SPRN_L2CSR1, (32 + 1));
669 /* enable the cache */
670 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
672 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
673 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
675 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
679 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
680 if (l2cache->l2csr0 & L2CSR0_L2E)
681 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
689 #if defined(CONFIG_RAMBOOT_PBL)
694 #ifndef CONFIG_SYS_FSL_NO_SERDES
695 /* needs to be in ram since code uses global static vars */
699 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
700 #define MCFGR_AXIPIPE 0x000000f0
701 if (IS_SVR_REV(svr, 1, 0))
702 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
705 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
706 if (IS_SVR_REV(svr, 1, 0)) {
708 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
710 for (i = 0; i < 12; i++) {
711 p += i + (i > 5 ? 11 : 0);
714 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
719 #ifdef CONFIG_SYS_SRIO
721 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
722 char *s = getenv("bootmaster");
724 if (!strcmp(s, "SRIO1")) {
726 srio_boot_master_release_slave(1);
728 if (!strcmp(s, "SRIO2")) {
730 srio_boot_master_release_slave(2);
736 #if defined(CONFIG_MP)
740 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
742 if (SVR_MAJ(svr) < 3) {
744 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
745 setbits_be32(p, 1 << (31 - 14));
750 #ifdef CONFIG_SYS_LBC_LCRR
752 * Modify the CLKDIV field of LCRR register to improve the writing
753 * speed for NOR flash.
755 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
756 __raw_readl(&lbc->lcrr);
758 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
763 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
765 struct ccsr_usb_phy __iomem *usb_phy1 =
766 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
767 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
768 if (has_erratum_a006261())
769 fsl_erratum_a006261_workaround(usb_phy1);
771 out_be32(&usb_phy1->usb_enable_override,
772 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
775 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
777 struct ccsr_usb_phy __iomem *usb_phy2 =
778 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
779 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
780 if (has_erratum_a006261())
781 fsl_erratum_a006261_workaround(usb_phy2);
783 out_be32(&usb_phy2->usb_enable_override,
784 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
788 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
789 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
790 * multi-bit ECC errors which has impact on performance, so software
791 * should disable all ECC reporting from USB1 and USB2.
793 if (IS_SVR_REV(get_svr(), 1, 0)) {
794 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
795 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
796 setbits_be32(&dcfg->ecccr1,
797 (DCSR_DCFG_ECC_DISABLE_USB1 |
798 DCSR_DCFG_ECC_DISABLE_USB2));
802 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
803 struct ccsr_usb_phy __iomem *usb_phy =
804 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
805 setbits_be32(&usb_phy->pllprg[1],
806 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
807 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
808 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
809 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
810 setbits_be32(&usb_phy->port1.ctrl,
811 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
812 setbits_be32(&usb_phy->port1.drvvbuscfg,
813 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
814 setbits_be32(&usb_phy->port1.pwrfltcfg,
815 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
816 setbits_be32(&usb_phy->port2.ctrl,
817 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
818 setbits_be32(&usb_phy->port2.drvvbuscfg,
819 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
820 setbits_be32(&usb_phy->port2.pwrfltcfg,
821 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
823 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
824 if (has_erratum_a006261())
825 fsl_erratum_a006261_workaround(usb_phy);
828 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
830 #ifdef CONFIG_FMAN_ENET
834 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
836 * For P1022/1013 Rev1.0 silicon, after power on SATA host
837 * controller is configured in legacy mode instead of the
838 * expected enterprise mode. Software needs to clear bit[28]
839 * of HControl register to change to enterprise mode from
840 * legacy mode. We assume that the controller is offline.
842 if (IS_SVR_REV(svr, 1, 0) &&
843 ((SVR_SOC_VER(svr) == SVR_P1022) ||
844 (SVR_SOC_VER(svr) == SVR_P1013))) {
847 /* first SATA controller */
848 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
849 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
851 /* second SATA controller */
852 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
853 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
861 void arch_preboot_os(void)
866 * We are changing interrupt offsets and are about to boot the OS so
867 * we need to make sure we disable all async interrupts. EE is already
868 * disabled by the time we get called.
871 msr &= ~(MSR_ME|MSR_CE);
875 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
876 int sata_initialize(void)
878 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
879 return __sata_initialize();
885 void cpu_secondary_init_r(void)
888 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
889 #elif defined CONFIG_QE
890 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
894 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
896 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
898 /* load QE firmware from NAND flash to DDR first */
899 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
900 &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
902 if (ret && ret == -EUCLEAN) {
903 printf ("NAND read for QE firmware at offset %x failed %d\n",
904 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);