2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/processor.h>
20 #include <asm/cache.h>
22 #include <asm/fsl_errata.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h>
28 #include <linux/compiler.h>
30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
35 #include "../../../../drivers/block/fsl_sata.h"
37 #include "../../../../drivers/qe/qe.h"
40 DECLARE_GLOBAL_DATA_PTR;
42 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
44 * For deriving usb clock from 100MHz sysclk, reference divisor is set
45 * to a value of 5, which gives an intermediate value 20(100/5). The
46 * multiplication factor integer is set to 24, which when multiplied to
47 * above intermediate value provides clock for usb ip.
49 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
53 get_sys_info(&sysinfo);
54 if (sysinfo.diff_sysclk == 1) {
55 clrbits_be32(&usb_phy->pllprg[1],
56 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
57 setbits_be32(&usb_phy->pllprg[1],
58 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
60 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
65 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
66 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
68 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
69 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
71 /* Increase Disconnect Threshold by 50mV */
72 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
73 INC_DCNT_THRESHOLD_50MV;
74 /* Enable programming of USB High speed Disconnect threshold */
75 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
76 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
78 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
79 /* Increase Disconnect Threshold by 50mV */
80 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
81 INC_DCNT_THRESHOLD_50MV;
82 /* Enable programming of USB High speed Disconnect threshold */
83 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
84 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
88 u32 status = in_be32(&usb_phy->status1);
90 u32 squelch_prog_rd_0_2 =
91 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
92 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
94 u32 squelch_prog_rd_3_5 =
95 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
96 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
98 setbits_be32(&usb_phy->config1,
99 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
100 setbits_be32(&usb_phy->config2,
101 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
103 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
104 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
106 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
113 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
114 extern qe_iop_conf_t qe_iop_conf_tab[];
115 extern void qe_config_iopin(u8 port, u8 pin, int dir,
116 int open_drain, int assign);
117 extern void qe_init(uint qe_base);
118 extern void qe_reset(void);
120 static void config_qe_ioports(void)
123 int dir, open_drain, assign;
126 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
127 port = qe_iop_conf_tab[i].port;
128 pin = qe_iop_conf_tab[i].pin;
129 dir = qe_iop_conf_tab[i].dir;
130 open_drain = qe_iop_conf_tab[i].open_drain;
131 assign = qe_iop_conf_tab[i].assign;
132 qe_config_iopin(port, pin, dir, open_drain, assign);
138 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
142 for (portnum = 0; portnum < 4; portnum++) {
149 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
150 iop_conf_t *eiopc = iopc + 32;
155 * index 0 refers to pin 31,
156 * index 31 refers to pin 0
158 while (iopc < eiopc) {
178 volatile ioport_t *iop = ioport_addr (cpm, portnum);
182 * the (somewhat confused) paragraph at the
183 * bottom of page 35-5 warns that there might
184 * be "unknown behaviour" when programming
185 * PSORx and PDIRx, if PPARx = 1, so I
186 * decided this meant I had to disable the
187 * dedicated function first, and enable it
191 iop->psor = (iop->psor & tpmsk) | psor;
192 iop->podr = (iop->podr & tpmsk) | podr;
193 iop->pdat = (iop->pdat & tpmsk) | pdat;
194 iop->pdir = (iop->pdir & tpmsk) | pdir;
201 #ifdef CONFIG_SYS_FSL_CPC
202 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
203 static void disable_cpc_sram(void)
207 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
209 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
210 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
211 /* find and disable LAW of SRAM */
212 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
214 if (law.index == -1) {
215 printf("\nFatal error happened\n");
218 disable_law(law.index);
220 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
221 out_be32(&cpc->cpccsr0, 0);
222 out_be32(&cpc->cpcsrcr0, 0);
228 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
230 #error POST memory test cannot be enabled with TDM
232 static void enable_tdm_law(void)
235 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
236 int tdm_hwconfig_enabled = 0;
239 * Extract hwconfig from environment since environment
240 * is not setup properly yet. Search for tdm entry in
243 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
245 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
246 /* If tdm is defined in hwconfig, set law for tdm workaround */
247 if (tdm_hwconfig_enabled)
248 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
254 static void enable_cpc(void)
259 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
261 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
262 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
263 size += CPC_CFG0_SZ_K(cpccfg0);
265 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
266 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
268 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
269 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
271 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
272 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
274 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
275 if (has_erratum_a006379()) {
276 setbits_be32(&cpc->cpchdbcr0,
277 CPC_HDBCR0_SPLRU_LEVEL_EN);
281 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
282 /* Read back to sync write */
283 in_be32(&cpc->cpccsr0);
287 puts("Corenet Platform Cache: ");
288 print_size(size * 1024, " enabled\n");
291 static void invalidate_cpc(void)
294 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
296 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
297 /* skip CPC when it used as all SRAM */
298 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
300 /* Flash invalidate the CPC and clear all the locks */
301 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
302 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
308 #define invalidate_cpc()
309 #endif /* CONFIG_SYS_FSL_CPC */
312 * Breathe some life into the CPU...
314 * Set up the memory map
315 * initialize a bunch of registers
318 #ifdef CONFIG_FSL_CORENET
319 static void corenet_tb_init(void)
321 volatile ccsr_rcpm_t *rcpm =
322 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
323 volatile ccsr_pic_t *pic =
324 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
325 u32 whoami = in_be32(&pic->whoami);
327 /* Enable the timebase register for this core */
328 out_be32(&rcpm->ctbenrl, (1 << whoami));
332 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
333 void fsl_erratum_a007212_workaround(void)
335 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
337 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
338 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
339 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
340 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
341 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
342 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
343 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
344 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
345 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
349 * Even this workaround applies to selected version of SoCs, it is
350 * safe to apply to all versions, with the limitation of odd ratios.
351 * If RCW has disabled DDR PLL, we have to apply this workaround,
352 * otherwise DDR will not work.
354 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
355 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
356 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
357 /* check if RCW sets ratio to 0, required by this workaround */
358 if (ddr_pll_ratio != 0)
360 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
361 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
362 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
363 /* check if reserved bits have the desired ratio */
364 if (ddr_pll_ratio == 0) {
365 printf("Error: Unknown DDR PLL ratio!\n");
370 setbits_be32(plldadcr1, 0x02000001);
371 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
372 setbits_be32(plldadcr2, 0x02000001);
373 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
374 setbits_be32(plldadcr3, 0x02000001);
377 setbits_be32(dpdovrcr4, 0xe0000000);
378 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
379 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
380 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
381 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
382 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
386 clrbits_be32(plldadcr1, 0x02000001);
387 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
388 clrbits_be32(plldadcr2, 0x02000001);
389 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
390 clrbits_be32(plldadcr3, 0x02000001);
393 clrbits_be32(dpdovrcr4, 0xe0000000);
397 ulong cpu_init_f(void)
400 extern void m8560_cpm_reset (void);
401 #ifdef CONFIG_SYS_DCSRBAR_PHYS
402 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
404 #if defined(CONFIG_SECURE_BOOT)
405 struct law_entry law;
407 #ifdef CONFIG_MPC8548
408 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
409 uint svr = get_svr();
412 * CPU2 errata workaround: A core hang possible while executing
413 * a msync instruction and a snoopable transaction from an I/O
414 * master tagged to make quick forward progress is present.
415 * Fixed in silicon rev 2.1.
417 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
418 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
424 #if defined(CONFIG_SECURE_BOOT)
425 /* Disable the LAW created for NOR flash by the PBI commands */
426 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
428 disable_law(law.index);
430 #if defined(CONFIG_SYS_CPC_REINIT_F)
436 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
439 init_early_memctl_regs();
441 #if defined(CONFIG_CPM2)
445 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
446 /* Config QE ioports */
450 #if defined(CONFIG_FSL_DMA)
453 #ifdef CONFIG_FSL_CORENET
456 init_used_tlb_cams();
458 /* Invalidate the CPC before DDR gets enabled */
461 #ifdef CONFIG_SYS_DCSRBAR_PHYS
462 /* set DCSRCR so that DCSR space is 1G */
463 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
464 in_be32(&gur->dcsrcr);
467 #ifdef CONFIG_SYS_DCSRBAR_PHYS
468 #ifdef CONFIG_DEEP_SLEEP
469 /* disable the console if boot from deep sleep */
470 if (in_be32(&gur->scrtsr[0]) & (1 << 3))
471 flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
474 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
475 fsl_erratum_a007212_workaround();
481 /* Implement a dummy function for those platforms w/o SERDES */
482 static void __fsl_serdes__init(void)
486 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
488 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
489 int enable_cluster_l2(void)
492 u32 cluster, svr = get_svr();
493 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
494 struct ccsr_cluster_l2 __iomem *l2cache;
496 /* only the L2 of first cluster should be enabled as expected on T4080,
497 * but there is no EOC in the first cluster as HW sake, so return here
498 * to skip enabling L2 cache of the 2nd cluster.
500 if (SVR_SOC_VER(svr) == SVR_T4080)
503 cluster = in_be32(&gur->tp_cluster[i].lower);
504 if (cluster & TP_CLUSTER_EOC)
507 /* The first cache has already been set up, so skip it */
510 /* Look through the remaining clusters, and set up their caches */
512 int j, cluster_valid = 0;
514 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
516 cluster = in_be32(&gur->tp_cluster[i].lower);
518 /* check that at least one core/accel is enabled in cluster */
519 for (j = 0; j < 4; j++) {
520 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
521 u32 type = in_be32(&gur->tp_ityp[idx]);
523 if (type & TP_ITYP_AV)
528 /* set stash ID to (cluster) * 2 + 32 + 1 */
529 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
531 printf("enable l2 for cluster %d %p\n", i, l2cache);
533 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
534 while ((in_be32(&l2cache->l2csr0)
535 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
537 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
540 } while (!(cluster & TP_CLUSTER_EOC));
547 * Initialize L2 as cache.
549 * The newer 8548, etc, parts have twice as much cache, but
550 * use the same bit-encoding as the older 8555, etc, parts.
555 __maybe_unused u32 svr = get_svr();
556 #ifdef CONFIG_SYS_LBC_LCRR
557 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
559 #ifdef CONFIG_L2_CACHE
560 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
561 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
562 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
564 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
565 extern int spin_table_compat;
568 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
569 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
571 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
572 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
574 * CPU22 and NMG_CPU_A011 share the same workaround.
575 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
576 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
577 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
578 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
579 * be disabled by hwconfig with syntax:
581 * fsl_cpu_a011:disable
583 extern int enable_cpu_a011_workaround;
584 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
585 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
587 char buffer[HWCONFIG_BUFFER_SIZE];
591 n = getenv_f("hwconfig", buffer, sizeof(buffer));
595 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
597 enable_cpu_a011_workaround = 0;
599 if (n >= HWCONFIG_BUFFER_SIZE) {
600 printf("fsl_cpu_a011 was not found. hwconfig variable "
601 "may be too long\n");
603 enable_cpu_a011_workaround =
604 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
605 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
608 if (enable_cpu_a011_workaround) {
610 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
614 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
616 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
617 * in write shadow mode. Checking DCWS before setting SPR 976.
619 if (mfspr(L1CSR2) & L1CSR2_DCWS)
620 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
623 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
624 spin = getenv("spin_table_compat");
625 if (spin && (*spin == 'n'))
626 spin_table_compat = 0;
628 spin_table_compat = 1;
633 #if defined(CONFIG_L2_CACHE)
634 volatile uint cache_ctl;
638 ver = SVR_SOC_VER(svr);
641 cache_ctl = l2cache->l2ctl;
643 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
644 if (cache_ctl & MPC85xx_L2CTL_L2E) {
645 /* Clear L2 SRAM memory-mapped base address */
646 out_be32(&l2cache->l2srbar0, 0x0);
647 out_be32(&l2cache->l2srbar1, 0x0);
649 /* set MBECCDIS=0, SBECCDIS=0 */
650 clrbits_be32(&l2cache->l2errdis,
651 (MPC85xx_L2ERRDIS_MBECC |
652 MPC85xx_L2ERRDIS_SBECC));
654 /* set L2E=0, L2SRAM=0 */
655 clrbits_be32(&l2cache->l2ctl,
657 MPC85xx_L2CTL_L2SRAM_ENTIRE));
661 l2siz_field = (cache_ctl >> 28) & 0x3;
663 switch (l2siz_field) {
665 printf(" unknown size (0x%08x)\n", cache_ctl);
669 if (ver == SVR_8540 || ver == SVR_8560 ||
670 ver == SVR_8541 || ver == SVR_8555) {
672 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
673 cache_ctl = 0xc4000000;
676 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
680 if (ver == SVR_8540 || ver == SVR_8560 ||
681 ver == SVR_8541 || ver == SVR_8555) {
683 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
684 cache_ctl = 0xc8000000;
687 /* set L2E=1, L2I=1, & L2SRAM=0 */
688 cache_ctl = 0xc0000000;
693 /* set L2E=1, L2I=1, & L2SRAM=0 */
694 cache_ctl = 0xc0000000;
698 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
699 puts("already enabled");
700 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
701 u32 l2srbar = l2cache->l2srbar0;
702 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
703 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
704 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
705 l2cache->l2srbar0 = l2srbar;
706 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
708 #endif /* CONFIG_SYS_INIT_L2_ADDR */
712 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
716 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
717 if (SVR_SOC_VER(svr) == SVR_P2040) {
722 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
724 /* invalidate the L2 cache */
725 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
726 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
729 #ifdef CONFIG_SYS_CACHE_STASHING
730 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
731 mtspr(SPRN_L2CSR1, (32 + 1));
734 /* enable the cache */
735 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
737 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
738 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
740 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
744 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
745 if (l2cache->l2csr0 & L2CSR0_L2E)
746 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
754 #if defined(CONFIG_RAMBOOT_PBL)
758 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
762 #ifndef CONFIG_SYS_FSL_NO_SERDES
763 /* needs to be in ram since code uses global static vars */
767 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
768 #define MCFGR_AXIPIPE 0x000000f0
769 if (IS_SVR_REV(svr, 1, 0))
770 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
773 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
774 if (IS_SVR_REV(svr, 1, 0)) {
776 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
778 for (i = 0; i < 12; i++) {
779 p += i + (i > 5 ? 11 : 0);
782 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
787 #ifdef CONFIG_SYS_SRIO
789 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
790 char *s = getenv("bootmaster");
792 if (!strcmp(s, "SRIO1")) {
794 srio_boot_master_release_slave(1);
796 if (!strcmp(s, "SRIO2")) {
798 srio_boot_master_release_slave(2);
804 #if defined(CONFIG_MP)
808 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
810 if (SVR_MAJ(svr) < 3) {
812 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
813 setbits_be32(p, 1 << (31 - 14));
818 #ifdef CONFIG_SYS_LBC_LCRR
820 * Modify the CLKDIV field of LCRR register to improve the writing
821 * speed for NOR flash.
823 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
824 __raw_readl(&lbc->lcrr);
826 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
831 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
833 struct ccsr_usb_phy __iomem *usb_phy1 =
834 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
835 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
836 if (has_erratum_a006261())
837 fsl_erratum_a006261_workaround(usb_phy1);
839 out_be32(&usb_phy1->usb_enable_override,
840 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
843 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
845 struct ccsr_usb_phy __iomem *usb_phy2 =
846 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
847 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
848 if (has_erratum_a006261())
849 fsl_erratum_a006261_workaround(usb_phy2);
851 out_be32(&usb_phy2->usb_enable_override,
852 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
856 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
857 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
858 * multi-bit ECC errors which has impact on performance, so software
859 * should disable all ECC reporting from USB1 and USB2.
861 if (IS_SVR_REV(get_svr(), 1, 0)) {
862 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
863 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
864 setbits_be32(&dcfg->ecccr1,
865 (DCSR_DCFG_ECC_DISABLE_USB1 |
866 DCSR_DCFG_ECC_DISABLE_USB2));
870 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
871 struct ccsr_usb_phy __iomem *usb_phy =
872 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
873 setbits_be32(&usb_phy->pllprg[1],
874 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
875 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
876 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
877 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
878 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
879 usb_single_source_clk_configure(usb_phy);
881 setbits_be32(&usb_phy->port1.ctrl,
882 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
883 setbits_be32(&usb_phy->port1.drvvbuscfg,
884 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
885 setbits_be32(&usb_phy->port1.pwrfltcfg,
886 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
887 setbits_be32(&usb_phy->port2.ctrl,
888 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
889 setbits_be32(&usb_phy->port2.drvvbuscfg,
890 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
891 setbits_be32(&usb_phy->port2.pwrfltcfg,
892 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
894 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
895 if (has_erratum_a006261())
896 fsl_erratum_a006261_workaround(usb_phy);
899 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
901 #ifdef CONFIG_FMAN_ENET
905 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
907 * For P1022/1013 Rev1.0 silicon, after power on SATA host
908 * controller is configured in legacy mode instead of the
909 * expected enterprise mode. Software needs to clear bit[28]
910 * of HControl register to change to enterprise mode from
911 * legacy mode. We assume that the controller is offline.
913 if (IS_SVR_REV(svr, 1, 0) &&
914 ((SVR_SOC_VER(svr) == SVR_P1022) ||
915 (SVR_SOC_VER(svr) == SVR_P1013))) {
918 /* first SATA controller */
919 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
920 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
922 /* second SATA controller */
923 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
924 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
928 init_used_tlb_cams();
933 void arch_preboot_os(void)
938 * We are changing interrupt offsets and are about to boot the OS so
939 * we need to make sure we disable all async interrupts. EE is already
940 * disabled by the time we get called.
943 msr &= ~(MSR_ME|MSR_CE);
947 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
948 int sata_initialize(void)
950 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
951 return __sata_initialize();
957 void cpu_secondary_init_r(void)
960 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
961 #elif defined CONFIG_QE
962 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */