2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/processor.h>
12 #include <asm/fsl_ddr_sdram.h>
14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
19 unsigned int ctrl_num)
23 ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
25 ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
26 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
27 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
37 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
39 * Set the DDR IO receiver to an acceptable bias point.
43 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
44 if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
45 SDRAM_CFG_SDRAM_TYPE_DDR2)
46 out_be32(&gur->ddrioovcr, 0x90000000);
48 out_be32(&gur->ddrioovcr, 0xA8000000);
52 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
54 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
55 out_be32(&ddr->cs0_config, regs->cs[i].config);
58 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
59 out_be32(&ddr->cs1_config, regs->cs[i].config);
62 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
63 out_be32(&ddr->cs2_config, regs->cs[i].config);
66 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
67 out_be32(&ddr->cs3_config, regs->cs[i].config);
71 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
72 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
73 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
74 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
75 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
76 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
77 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
78 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
79 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
80 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
81 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
82 out_be32(&ddr->init_addr, regs->ddr_init_addr);
83 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
86 * 200 painful micro-seconds must elapse between
87 * the DDR clock setup and the DDR config enable.
90 asm volatile("sync;isync");
92 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
94 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
95 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
96 udelay(10000); /* throttle polling rate */