2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_ddr_sdram.h>
12 #include <asm/processor.h>
14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
19 unsigned int ctrl_num)
22 volatile ccsr_ddr_t *ddr;
24 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
25 volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
26 u32 total_gb_size_per_controller;
27 unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
33 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
36 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
39 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
43 out_be32(&ddr->eor, regs->ddr_eor);
45 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
46 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
47 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
48 cs_ea = regs->cs[i].bnds & 0xfff;
49 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
51 csn_bnds_backup = regs->cs[i].bnds;
52 csn_bnds_t = (unsigned int *) ®s->cs[i].bnds;
54 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
56 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
57 debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
58 "change it to 0x%x\n",
59 csn, csn_bnds_backup, regs->cs[i].bnds);
64 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
66 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
67 out_be32(&ddr->cs0_config, regs->cs[i].config);
68 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
71 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
72 out_be32(&ddr->cs1_config, regs->cs[i].config);
73 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
76 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
77 out_be32(&ddr->cs2_config, regs->cs[i].config);
78 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
81 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
82 out_be32(&ddr->cs3_config, regs->cs[i].config);
83 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
87 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
88 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
89 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
90 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
91 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
92 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
93 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
94 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
95 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
96 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
97 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
98 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
99 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
100 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
101 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
102 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
103 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
104 out_be32(&ddr->init_addr, regs->ddr_init_addr);
105 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
107 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
108 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
109 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
110 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
111 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
112 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
113 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
114 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
115 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
116 out_be32(&ddr->err_disable, regs->err_disable);
117 out_be32(&ddr->err_int_en, regs->err_int_en);
118 for (i = 0; i < 32; i++)
119 out_be32(&ddr->debug[i], regs->debug[i]);
121 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
122 out_be32(&ddr->debug[12], 0x00000015);
123 out_be32(&ddr->debug[21], 0x24000000);
124 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
126 /* Set, but do not enable the memory */
127 temp_sdram_cfg = regs->ddr_sdram_cfg;
128 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
129 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
130 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
131 if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
132 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
133 out_be32(&ddr->debug[2], 0x00000400);
134 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
135 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
136 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
137 out_be32(&ddr->mtcr, 0);
138 out_be32(&ddr->debug[12], 0x00000015);
139 out_be32(&ddr->debug[21], 0x24000000);
140 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
141 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
143 asm volatile("sync;isync");
144 while (!(in_be32(&ddr->debug[1]) & 0x2))
147 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
149 out_be32(&ddr->sdram_md_cntl,
151 MD_CNTL_CS_SEL_CS0_CS1 |
154 MD_CNTL_MD_VALUE(0x02));
157 out_be32(&ddr->sdram_md_cntl,
159 MD_CNTL_CS_SEL_CS0_CS1 |
162 MD_CNTL_MD_VALUE(0x0a));
165 out_be32(&ddr->sdram_md_cntl,
167 MD_CNTL_CS_SEL_CS0_CS1 |
170 MD_CNTL_MD_VALUE(0x12));
173 out_be32(&ddr->sdram_md_cntl,
175 MD_CNTL_CS_SEL_CS0_CS1 |
178 MD_CNTL_MD_VALUE(0x1a));
181 out_be32(&ddr->sdram_md_cntl,
183 MD_CNTL_CS_SEL_CS0_CS1 |
186 MD_CNTL_MD_VALUE(0x02));
187 printf("Unsupported RC10\n");
191 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
194 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
195 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
196 out_be32(&ddr->debug[2], 0x0);
197 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
198 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
199 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
200 out_be32(&ddr->debug[12], 0x0);
201 out_be32(&ddr->debug[21], 0x0);
202 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
207 * For 8572 DDR1 erratum - DDR controller may enter illegal state
208 * when operatiing in 32-bit bus mode with 4-beat bursts,
209 * This erratum does not affect DDR3 mode, only for DDR2 mode.
211 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
212 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
213 && in_be32(&ddr->sdram_cfg) & 0x80000) {
214 /* set DEBUG_1[31] */
215 setbits_be32(&ddr->debug[0], 1);
218 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
220 * This is the combined workaround for DDR111 and DDR134
221 * following the published errata for MPC8572
224 /* 1. Set EEBACR[3] */
225 setbits_be32(&ecm->eebacr, 0x10000000);
226 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
228 /* 2. Set DINIT in SDRAM_CFG_2*/
229 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
230 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
231 in_be32(&ddr->sdram_cfg_2));
233 /* 3. Set DEBUG_3[21] */
234 setbits_be32(&ddr->debug[2], 0x400);
235 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
237 #endif /* part 1 of the workaound */
240 * 500 painful micro-seconds must elapse between
241 * the DDR clock setup and the DDR config enable.
242 * DDR2 need 200 us, and DDR3 need 500 us from spec,
243 * we choose the max, that is 500 us for all of case.
246 asm volatile("sync;isync");
248 /* Let the controller go */
249 temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
250 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
251 asm volatile("sync;isync");
253 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
254 while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
255 udelay(10000); /* throttle polling rate */
257 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
258 /* continue this workaround */
260 /* 4. Clear DEBUG3[21] */
261 clrbits_be32(&ddr->debug[2], 0x400);
262 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
264 /* DDR134 workaround starts */
265 /* A: Clear sdram_cfg_2[odt_cfg] */
266 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
267 debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
268 in_be32(&ddr->sdram_cfg_2));
270 /* B: Set DEBUG1[15] */
271 setbits_be32(&ddr->debug[0], 0x10000);
272 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
274 /* C: Set timing_cfg_2[cpo] to 0b11111 */
275 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
276 debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
277 in_be32(&ddr->timing_cfg_2));
279 /* D: Set D6 to 0x9f9f9f9f */
280 out_be32(&ddr->debug[5], 0x9f9f9f9f);
281 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
283 /* E: Set D7 to 0x9f9f9f9f */
284 out_be32(&ddr->debug[6], 0x9f9f9f9f);
285 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
288 setbits_be32(&ddr->debug[1], 0x800);
289 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
291 /* G: Poll on D2[20] until cleared */
292 while (in_be32(&ddr->debug[1]) & 0x800)
293 udelay(10000); /* throttle polling rate */
295 /* H: Clear D1[15] */
296 clrbits_be32(&ddr->debug[0], 0x10000);
297 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
299 /* I: Set sdram_cfg_2[odt_cfg] */
300 setbits_be32(&ddr->sdram_cfg_2,
301 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
302 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
304 /* Continuing with the DDR111 workaround */
306 setbits_be32(&ddr->debug[1], 0x400);
307 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
309 /* 6. Poll D2[21] until its cleared */
310 while (in_be32(&ddr->debug[1]) & 0x400)
311 udelay(10000); /* throttle polling rate */
313 /* 7. Wait for 400ms/GB */
314 total_gb_size_per_controller = 0;
315 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
317 total_gb_size_per_controller +=
318 ((csn_bnds_backup & 0xFFFF) >> 6)
319 - (csn_bnds_backup >> 22) + 1;
321 total_gb_size_per_controller +=
322 ((regs->cs[i].bnds & 0xFFFF) >> 6)
323 - (regs->cs[i].bnds >> 22) + 1;
326 if (in_be32(&ddr->sdram_cfg) & 0x80000)
327 total_gb_size_per_controller <<= 1;
328 debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
329 udelay(total_gb_size_per_controller * 400000);
331 /* 8. Set sdram_cfg_2[dinit] if options requires */
332 setbits_be32(&ddr->sdram_cfg_2,
333 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
334 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
336 /* 9. Poll until dinit is cleared */
337 while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
340 /* 10. Clear EEBACR[3] */
341 clrbits_be32(&ecm->eebacr, 10000000);
342 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
345 csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds;
346 *csn_bnds_t = csn_bnds_backup;
347 debug("Change cs%d_bnds back to 0x%08x\n",
348 csn, regs->cs[csn].bnds);
349 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */
352 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
355 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
358 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
361 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
364 clrbits_be32(&ddr->sdram_cfg, 0x2);
366 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */