2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_ddr_sdram.h>
12 #include <asm/processor.h>
14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
19 unsigned int ctrl_num)
22 volatile ccsr_ddr_t *ddr;
24 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
25 volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
26 u32 total_gb_size_per_controller;
27 unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
33 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
35 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
37 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
40 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
42 ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
45 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
47 ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
51 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
55 out_be32(&ddr->eor, regs->ddr_eor);
57 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
58 debug("Workaround for ERRATUM_DDR111_DDR134\n");
59 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
60 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
61 cs_ea = regs->cs[i].bnds & 0xfff;
62 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
64 csn_bnds_backup = regs->cs[i].bnds;
65 csn_bnds_t = (unsigned int *) ®s->cs[i].bnds;
67 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
69 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
70 debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
71 "change it to 0x%x\n",
72 csn, csn_bnds_backup, regs->cs[i].bnds);
77 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
79 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
80 out_be32(&ddr->cs0_config, regs->cs[i].config);
81 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
84 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
85 out_be32(&ddr->cs1_config, regs->cs[i].config);
86 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
89 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
90 out_be32(&ddr->cs2_config, regs->cs[i].config);
91 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
94 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
95 out_be32(&ddr->cs3_config, regs->cs[i].config);
96 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
100 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
101 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
102 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
103 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
104 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
105 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
106 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
107 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
108 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
109 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
110 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
111 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
112 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
113 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
114 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
115 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
116 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
117 out_be32(&ddr->init_addr, regs->ddr_init_addr);
118 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
120 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
121 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
122 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
123 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
124 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
125 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
126 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
127 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
128 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
129 out_be32(&ddr->err_disable, regs->err_disable);
130 out_be32(&ddr->err_int_en, regs->err_int_en);
131 for (i = 0; i < 32; i++) {
132 if (regs->debug[i]) {
133 debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
134 out_be32(&ddr->debug[i], regs->debug[i]);
138 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
139 out_be32(&ddr->debug[12], 0x00000015);
140 out_be32(&ddr->debug[21], 0x24000000);
141 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
143 /* Set, but do not enable the memory */
144 temp_sdram_cfg = regs->ddr_sdram_cfg;
145 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
146 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
147 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
148 debug("Workaround for ERRATUM_DDR_A003\n");
149 if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
150 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
151 out_be32(&ddr->debug[2], 0x00000400);
152 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
153 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
154 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
155 out_be32(&ddr->mtcr, 0);
156 out_be32(&ddr->debug[12], 0x00000015);
157 out_be32(&ddr->debug[21], 0x24000000);
158 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
159 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
161 asm volatile("sync;isync");
162 while (!(in_be32(&ddr->debug[1]) & 0x2))
165 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
167 out_be32(&ddr->sdram_md_cntl,
169 MD_CNTL_CS_SEL_CS0_CS1 |
172 MD_CNTL_MD_VALUE(0x02));
175 out_be32(&ddr->sdram_md_cntl,
177 MD_CNTL_CS_SEL_CS0_CS1 |
180 MD_CNTL_MD_VALUE(0x0a));
183 out_be32(&ddr->sdram_md_cntl,
185 MD_CNTL_CS_SEL_CS0_CS1 |
188 MD_CNTL_MD_VALUE(0x12));
191 out_be32(&ddr->sdram_md_cntl,
193 MD_CNTL_CS_SEL_CS0_CS1 |
196 MD_CNTL_MD_VALUE(0x1a));
199 out_be32(&ddr->sdram_md_cntl,
201 MD_CNTL_CS_SEL_CS0_CS1 |
204 MD_CNTL_MD_VALUE(0x02));
205 printf("Unsupported RC10\n");
209 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
212 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
213 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
214 out_be32(&ddr->debug[2], 0x0);
215 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
216 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
217 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
218 out_be32(&ddr->debug[12], 0x0);
219 out_be32(&ddr->debug[21], 0x0);
220 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
225 * For 8572 DDR1 erratum - DDR controller may enter illegal state
226 * when operatiing in 32-bit bus mode with 4-beat bursts,
227 * This erratum does not affect DDR3 mode, only for DDR2 mode.
229 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
230 debug("Workaround for ERRATUM_DDR_115\n");
231 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
232 && in_be32(&ddr->sdram_cfg) & 0x80000) {
233 /* set DEBUG_1[31] */
234 setbits_be32(&ddr->debug[0], 1);
237 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
238 debug("Workaround for ERRATUM_DDR111_DDR134\n");
240 * This is the combined workaround for DDR111 and DDR134
241 * following the published errata for MPC8572
244 /* 1. Set EEBACR[3] */
245 setbits_be32(&ecm->eebacr, 0x10000000);
246 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
248 /* 2. Set DINIT in SDRAM_CFG_2*/
249 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
250 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
251 in_be32(&ddr->sdram_cfg_2));
253 /* 3. Set DEBUG_3[21] */
254 setbits_be32(&ddr->debug[2], 0x400);
255 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
257 #endif /* part 1 of the workaound */
260 * 500 painful micro-seconds must elapse between
261 * the DDR clock setup and the DDR config enable.
262 * DDR2 need 200 us, and DDR3 need 500 us from spec,
263 * we choose the max, that is 500 us for all of case.
266 asm volatile("sync;isync");
268 /* Let the controller go */
269 temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
270 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
271 asm volatile("sync;isync");
273 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
274 while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
275 udelay(10000); /* throttle polling rate */
277 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
278 /* continue this workaround */
280 /* 4. Clear DEBUG3[21] */
281 clrbits_be32(&ddr->debug[2], 0x400);
282 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
284 /* DDR134 workaround starts */
285 /* A: Clear sdram_cfg_2[odt_cfg] */
286 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
287 debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
288 in_be32(&ddr->sdram_cfg_2));
290 /* B: Set DEBUG1[15] */
291 setbits_be32(&ddr->debug[0], 0x10000);
292 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
294 /* C: Set timing_cfg_2[cpo] to 0b11111 */
295 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
296 debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
297 in_be32(&ddr->timing_cfg_2));
299 /* D: Set D6 to 0x9f9f9f9f */
300 out_be32(&ddr->debug[5], 0x9f9f9f9f);
301 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
303 /* E: Set D7 to 0x9f9f9f9f */
304 out_be32(&ddr->debug[6], 0x9f9f9f9f);
305 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
308 setbits_be32(&ddr->debug[1], 0x800);
309 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
311 /* G: Poll on D2[20] until cleared */
312 while (in_be32(&ddr->debug[1]) & 0x800)
313 udelay(10000); /* throttle polling rate */
315 /* H: Clear D1[15] */
316 clrbits_be32(&ddr->debug[0], 0x10000);
317 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
319 /* I: Set sdram_cfg_2[odt_cfg] */
320 setbits_be32(&ddr->sdram_cfg_2,
321 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
322 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
324 /* Continuing with the DDR111 workaround */
326 setbits_be32(&ddr->debug[1], 0x400);
327 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
329 /* 6. Poll D2[21] until its cleared */
330 while (in_be32(&ddr->debug[1]) & 0x400)
331 udelay(10000); /* throttle polling rate */
333 /* 7. Wait for 400ms/GB */
334 total_gb_size_per_controller = 0;
335 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
337 total_gb_size_per_controller +=
338 ((csn_bnds_backup & 0xFFFF) >> 6)
339 - (csn_bnds_backup >> 22) + 1;
341 total_gb_size_per_controller +=
342 ((regs->cs[i].bnds & 0xFFFF) >> 6)
343 - (regs->cs[i].bnds >> 22) + 1;
346 if (in_be32(&ddr->sdram_cfg) & 0x80000)
347 total_gb_size_per_controller <<= 1;
348 debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
349 udelay(total_gb_size_per_controller * 400000);
351 /* 8. Set sdram_cfg_2[dinit] if options requires */
352 setbits_be32(&ddr->sdram_cfg_2,
353 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
354 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
356 /* 9. Poll until dinit is cleared */
357 while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
360 /* 10. Clear EEBACR[3] */
361 clrbits_be32(&ecm->eebacr, 10000000);
362 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
365 csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds;
366 *csn_bnds_t = csn_bnds_backup;
367 debug("Change cs%d_bnds back to 0x%08x\n",
368 csn, regs->cs[csn].bnds);
369 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */
372 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
375 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
378 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
381 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
384 clrbits_be32(&ddr->sdram_cfg, 0x2);
386 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */