2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_ddr_sdram.h>
12 #include <asm/processor.h>
14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
19 unsigned int ctrl_num)
22 volatile ccsr_ddr_t *ddr;
27 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
30 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
33 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
37 out_be32(&ddr->eor, regs->ddr_eor);
39 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
41 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
42 out_be32(&ddr->cs0_config, regs->cs[i].config);
43 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
46 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
47 out_be32(&ddr->cs1_config, regs->cs[i].config);
48 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
51 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
52 out_be32(&ddr->cs2_config, regs->cs[i].config);
53 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
56 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
57 out_be32(&ddr->cs3_config, regs->cs[i].config);
58 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
62 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
63 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
64 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
65 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
66 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
67 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
68 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
69 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
70 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
71 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
72 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
73 out_be32(&ddr->init_addr, regs->ddr_init_addr);
74 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
76 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
77 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
78 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
79 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
80 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
81 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
82 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
83 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
84 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
85 out_be32(&ddr->err_disable, regs->err_disable);
86 out_be32(&ddr->err_int_en, regs->err_int_en);
87 for (i = 0; i < 32; i++)
88 out_be32(&ddr->debug[i], regs->debug[i]);
90 /* Set, but do not enable the memory */
91 temp_sdram_cfg = regs->ddr_sdram_cfg;
92 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
93 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
95 * For 8572 DDR1 erratum - DDR controller may enter illegal state
96 * when operatiing in 32-bit bus mode with 4-beat bursts,
97 * This erratum does not affect DDR3 mode, only for DDR2 mode.
100 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
101 && in_be32(&ddr->sdram_cfg) & 0x80000) {
102 /* set DEBUG_1[31] */
103 setbits_be32(&ddr->debug[0], 1);
108 * 500 painful micro-seconds must elapse between
109 * the DDR clock setup and the DDR config enable.
110 * DDR2 need 200 us, and DDR3 need 500 us from spec,
111 * we choose the max, that is 500 us for all of case.
114 asm volatile("sync;isync");
116 /* Let the controller go */
117 temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
118 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
120 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
121 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
122 udelay(10000); /* throttle polling rate */