2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/fsl_serdes.h>
9 #include <asm/immap_85xx.h>
11 #include <asm/processor.h>
12 #include <asm/fsl_law.h>
13 #include <asm/errno.h>
14 #include "fsl_corenet2_serdes.h"
16 #ifdef CONFIG_SYS_FSL_SRDS_1
17 static u64 serdes1_prtcl_map;
19 #ifdef CONFIG_SYS_FSL_SRDS_2
20 static u64 serdes2_prtcl_map;
22 #ifdef CONFIG_SYS_FSL_SRDS_3
23 static u64 serdes3_prtcl_map;
25 #ifdef CONFIG_SYS_FSL_SRDS_4
26 static u64 serdes4_prtcl_map;
30 static const char *serdes_prtcl_str[] = {
40 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
41 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
42 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
43 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
44 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
45 [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
46 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
47 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
48 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
49 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
50 [XAUI_FM1] = "XAUI_FM1",
51 [XAUI_FM2] = "XAUI_FM2",
61 [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
62 [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
63 [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
64 [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
65 [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
66 [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
67 [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
68 [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
69 [QSGMII_FM1_A] = "QSGMII_FM1_A",
70 [QSGMII_FM1_B] = "QSGMII_FM1_B",
71 [QSGMII_FM2_A] = "QSGMII_FM2_A",
72 [QSGMII_FM2_B] = "QSGMII_FM2_B",
73 [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
74 [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
75 [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
76 [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
77 [INTERLAKEN] = "INTERLAKEN",
78 [QSGMII_SW1_A] = "QSGMII_SW1_A",
79 [QSGMII_SW1_B] = "QSGMII_SW1_B",
83 int is_serdes_configured(enum srds_prtcl device)
87 #ifdef CONFIG_SYS_FSL_SRDS_1
88 ret |= (1ULL << device) & serdes1_prtcl_map;
90 #ifdef CONFIG_SYS_FSL_SRDS_2
91 ret |= (1ULL << device) & serdes2_prtcl_map;
93 #ifdef CONFIG_SYS_FSL_SRDS_3
94 ret |= (1ULL << device) & serdes3_prtcl_map;
96 #ifdef CONFIG_SYS_FSL_SRDS_4
97 ret |= (1ULL << device) & serdes4_prtcl_map;
103 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
105 const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
106 u32 cfg = in_be32(&gur->rcwsr[4]);
110 #ifdef CONFIG_SYS_FSL_SRDS_1
112 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
113 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
116 #ifdef CONFIG_SYS_FSL_SRDS_2
118 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
119 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
122 #ifdef CONFIG_SYS_FSL_SRDS_3
124 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
125 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
128 #ifdef CONFIG_SYS_FSL_SRDS_4
130 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
131 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
135 printf("invalid SerDes%d\n", sd);
138 /* Is serdes enabled at all? */
139 if (unlikely(cfg == 0))
142 for (i = 0; i < SRDS_MAX_LANES; i++) {
143 if (serdes_get_prtcl(sd, cfg, i) == device)
150 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
152 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
153 u64 serdes_prtcl_map = 0;
157 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
158 /* Is serdes enabled at all? */
160 printf("SERDES%d is not enabled\n", sd + 1);
164 cfg >>= sd_prctl_shift;
165 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
166 if (!is_serdes_prtcl_valid(sd, cfg))
167 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
169 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
170 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
171 serdes_prtcl_map |= (1ULL << lane_prtcl);
174 return serdes_prtcl_map;
177 void fsl_serdes_init(void)
180 #ifdef CONFIG_SYS_FSL_SRDS_1
181 serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
182 CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
183 FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
184 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
186 #ifdef CONFIG_SYS_FSL_SRDS_2
187 serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
188 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
189 FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
190 FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
192 #ifdef CONFIG_SYS_FSL_SRDS_3
193 serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
194 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
195 FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
196 FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
198 #ifdef CONFIG_SYS_FSL_SRDS_4
199 serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
200 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
201 FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
202 FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
207 const char *serdes_clock_to_string(u32 clock)
210 case SRDS_PLLCR0_RFCK_SEL_100:
212 case SRDS_PLLCR0_RFCK_SEL_125:
214 case SRDS_PLLCR0_RFCK_SEL_156_25:
216 case SRDS_PLLCR0_RFCK_SEL_161_13:
217 return "161.1328123";
219 #if defined(CONFIG_T4240QDS)