2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/fsl_serdes.h>
9 #include <asm/immap_85xx.h>
11 #include <asm/processor.h>
12 #include <asm/fsl_law.h>
13 #include <asm/errno.h>
14 #include "fsl_corenet2_serdes.h"
16 #ifdef CONFIG_SYS_FSL_SRDS_1
17 static u64 serdes1_prtcl_map;
19 #ifdef CONFIG_SYS_FSL_SRDS_2
20 static u64 serdes2_prtcl_map;
22 #ifdef CONFIG_SYS_FSL_SRDS_3
23 static u64 serdes3_prtcl_map;
25 #ifdef CONFIG_SYS_FSL_SRDS_4
26 static u64 serdes4_prtcl_map;
30 static const char *serdes_prtcl_str[] = {
40 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
41 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
42 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
43 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
44 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
45 [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
46 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
47 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
48 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
49 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
50 [XAUI_FM1] = "XAUI_FM1",
51 [XAUI_FM2] = "XAUI_FM2",
61 [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
62 [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
63 [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
64 [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
65 [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
66 [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
67 [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
68 [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
69 [QSGMII_FM1_A] = "QSGMII_FM1_A",
70 [QSGMII_FM1_B] = "QSGMII_FM1_B",
71 [QSGMII_FM2_A] = "QSGMII_FM2_A",
72 [QSGMII_FM2_B] = "QSGMII_FM2_B",
73 [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
74 [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
75 [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
76 [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
77 [INTERLAKEN] = "INTERLAKEN",
78 [QSGMII_SW1_A] = "QSGMII_SW1_A",
79 [QSGMII_SW1_B] = "QSGMII_SW1_B",
83 int is_serdes_configured(enum srds_prtcl device)
87 #ifdef CONFIG_SYS_FSL_SRDS_1
88 ret |= (1ULL << device) & serdes1_prtcl_map;
90 #ifdef CONFIG_SYS_FSL_SRDS_2
91 ret |= (1ULL << device) & serdes2_prtcl_map;
93 #ifdef CONFIG_SYS_FSL_SRDS_3
94 ret |= (1ULL << device) & serdes3_prtcl_map;
96 #ifdef CONFIG_SYS_FSL_SRDS_4
97 ret |= (1ULL << device) & serdes4_prtcl_map;
103 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
105 const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
106 u32 cfg = in_be32(&gur->rcwsr[4]);
110 #ifdef CONFIG_SYS_FSL_SRDS_1
112 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
113 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
116 #ifdef CONFIG_SYS_FSL_SRDS_2
118 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
119 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
122 #ifdef CONFIG_SYS_FSL_SRDS_3
124 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
125 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
128 #ifdef CONFIG_SYS_FSL_SRDS_4
130 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
131 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
135 printf("invalid SerDes%d\n", sd);
138 /* Is serdes enabled at all? */
139 if (unlikely(cfg == 0))
142 for (i = 0; i < SRDS_MAX_LANES; i++) {
143 if (serdes_get_prtcl(sd, cfg, i) == device)
163 #define FUSE_VAL_MASK 0x00000003
164 #define FUSE_VAL_SHIFT 30
165 #define CR0_DCBIAS_SHIFT 5
166 #define CR1_FCAP_SHIFT 15
167 #define CR1_BCAP_SHIFT 29
168 #define FCAP_MASK 0x001F8000
169 #define BCAP_MASK 0x20000000
170 #define BCAP_OVD_MASK 0x10000000
171 #define BYP_CAL_MASK 0x02000000
173 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
175 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
176 u64 serdes_prtcl_map = 0;
179 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
180 struct ccsr_sfp_regs __iomem *sfp_regs =
181 (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
182 u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
183 u32 bc_status, fc_status, dc_status, pll_sr2;
184 serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
188 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
191 * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
192 * The workaround requires factory pre-set SerDes calibration values to be
193 * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
194 * These values have been shown to work across the
195 * entire temperature range for all SerDes. These values are then written into
196 * the SerDes registers to calibrate the SerDes PLL.
198 * This workaround for the protocols and rates that only have the Ring VCO.
200 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
201 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
202 debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
204 sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
206 if (sel == 0x01 || sel == 0x02) {
207 for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
208 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
209 debug("A007186: pll_num=%x pllcr0=%x\n",
210 pll_num, pll_status);
212 /* Read factory pre-set SerDes calibration values
213 * from fuse block(SFP scratch register-sfp_spfr0)
215 switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
216 case SRDS_PLLCR0_FRATE_SEL_3_0:
217 case SRDS_PLLCR0_FRATE_SEL_3_072:
218 debug("A007186: 3.0/3.072 protocol rate\n");
219 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
220 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
221 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
223 case SRDS_PLLCR0_FRATE_SEL_3_125:
224 debug("A007186: 3.125 protocol rate\n");
225 bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
226 dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
227 fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
229 case SRDS_PLLCR0_FRATE_SEL_3_75:
230 debug("A007186: 3.75 protocol rate\n");
231 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
232 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
233 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
240 /* Write SRDSxPLLnCR1[11:16] = FC
241 * Write SRDSxPLLnCR1[2] = BC
243 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
244 pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
245 ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
246 out_be32(&srds_regs->bank[pll_num].pllcr1,
247 (pll_cr_upd | pll_cr1));
248 debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
249 pll_num, (pll_cr_upd | pll_cr1));
250 /* Write SRDSxPLLnCR0[24:26] = DC
252 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
253 out_be32(&srds_regs->bank[pll_num].pllcr0,
254 pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
255 debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
256 pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
257 /* Write SRDSxPLLnCR1[3] = 1
258 * Write SRDSxPLLnCR1[6] = 1
260 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
261 pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
262 out_be32(&srds_regs->bank[pll_num].pllcr1,
263 (pll_cr_upd | pll_cr1));
264 debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
265 pll_num, (pll_cr_upd | pll_cr1));
268 /* Read the status Registers */
269 /* Verify SRDSxPLLnSR2[8] = BC */
270 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
271 debug("A007186: pll_num=%x pllsr2=%x\n",
273 bc_status = (pll_sr2 >> 23) & BC_MASK;
275 debug("BC mismatch\n");
276 fc_status = (pll_sr2 >> 16) & FC_MASK;
278 debug("FC mismatch\n");
279 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
280 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
282 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
283 dc_status = (pll_sr2 >> 17) & DC_MASK;
285 debug("DC mismatch\n");
286 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
287 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
291 /* Wait 750us to verify the PLL is locked
292 * by checking SRDSxPLLnCR0[8] = 1.
295 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
296 debug("A007186: pll_num=%x pllcr0=%x\n",
297 pll_num, pll_status);
299 if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
300 printf("A007186 Serdes PLL not locked\n");
302 debug("A007186 Serdes PLL locked\n");
307 cfg >>= sd_prctl_shift;
308 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
309 if (!is_serdes_prtcl_valid(sd, cfg))
310 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
312 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
313 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
314 serdes_prtcl_map |= (1ULL << lane_prtcl);
317 return serdes_prtcl_map;
320 void fsl_serdes_init(void)
323 #ifdef CONFIG_SYS_FSL_SRDS_1
324 serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
325 CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
326 FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
327 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
329 #ifdef CONFIG_SYS_FSL_SRDS_2
330 serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
331 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
332 FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
333 FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
335 #ifdef CONFIG_SYS_FSL_SRDS_3
336 serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
337 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
338 FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
339 FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
341 #ifdef CONFIG_SYS_FSL_SRDS_4
342 serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
343 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
344 FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
345 FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
350 const char *serdes_clock_to_string(u32 clock)
353 case SRDS_PLLCR0_RFCK_SEL_100:
355 case SRDS_PLLCR0_RFCK_SEL_125:
357 case SRDS_PLLCR0_RFCK_SEL_156_25:
359 case SRDS_PLLCR0_RFCK_SEL_161_13:
360 return "161.1328123";
362 #if defined(CONFIG_T4240QDS)