2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
27 #include <asm/fsl_serdes.h>
28 #include <asm/immap_85xx.h>
30 #include <asm/processor.h>
31 #include <asm/fsl_law.h>
32 #include <asm/errno.h>
33 #include "fsl_corenet_serdes.h"
36 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
37 * The code is already very complicated as it is, and separating the two
38 * completely would just make things worse. We try to keep them as separate
39 * as possible, but for now we require SERDES8 if SERDES_A001 is defined.
41 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
42 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
43 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
47 static u32 serdes_prtcl_map;
49 #define HWCONFIG_BUFFER_SIZE 128
52 static const char *serdes_prtcl_str[] = {
62 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
63 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
64 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
65 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
66 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
67 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
68 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
69 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
70 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
71 [XAUI_FM1] = "XAUI_FM1",
72 [XAUI_FM2] = "XAUI_FM2",
79 unsigned int lpd; /* RCW lane powerdown bit */
81 } lanes[SRDS_MAX_LANES] = {
82 { 0, 152, FSL_SRDS_BANK_1 },
83 { 1, 153, FSL_SRDS_BANK_1 },
84 { 2, 154, FSL_SRDS_BANK_1 },
85 { 3, 155, FSL_SRDS_BANK_1 },
86 { 4, 156, FSL_SRDS_BANK_1 },
87 { 5, 157, FSL_SRDS_BANK_1 },
88 { 6, 158, FSL_SRDS_BANK_1 },
89 { 7, 159, FSL_SRDS_BANK_1 },
90 { 8, 160, FSL_SRDS_BANK_1 },
91 { 9, 161, FSL_SRDS_BANK_1 },
92 { 16, 162, FSL_SRDS_BANK_2 },
93 { 17, 163, FSL_SRDS_BANK_2 },
94 { 18, 164, FSL_SRDS_BANK_2 },
95 { 19, 165, FSL_SRDS_BANK_2 },
96 { 20, 170, FSL_SRDS_BANK_3 },
97 { 21, 171, FSL_SRDS_BANK_3 },
98 { 22, 172, FSL_SRDS_BANK_3 },
99 { 23, 173, FSL_SRDS_BANK_3 },
102 int serdes_get_lane_idx(int lane)
104 return lanes[lane].idx;
107 int serdes_get_bank_by_lane(int lane)
109 return lanes[lane].bank;
112 int serdes_lane_enabled(int lane)
114 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
115 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
117 int bank = lanes[lane].bank;
118 int word = lanes[lane].lpd / 32;
119 int bit = lanes[lane].lpd % 32;
121 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
124 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
126 * For banks two and three, use the srds_lpd_b[] array instead of the
127 * RCW, because this array contains the real values of SRDS_LPD_B2 and
131 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
134 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
137 int is_serdes_configured(enum srds_prtcl device)
139 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
141 /* Is serdes enabled at all? */
142 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
145 return (1 << device) & serdes_prtcl_map;
148 static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
152 for (i = 0; i < SRDS_MAX_LANES; i++) {
153 if (serdes_get_prtcl(prtcl, i) == device)
161 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
162 * device. This depends on the current SERDES protocol, as defined in the RCW.
164 * Returns a negative error code if SERDES is disabled or the given device is
165 * not supported in the current SERDES protocol.
167 int serdes_get_first_lane(enum srds_prtcl device)
170 const ccsr_gur_t *gur;
172 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
174 /* Is serdes enabled at all? */
175 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
178 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
180 return __serdes_get_first_lane(prtcl, device);
183 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
185 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
188 * Returns a negative error code if the given device is not supported for the
189 * given SERDES protocol.
191 static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
195 lane = __serdes_get_first_lane(prtcl, device);
196 if (unlikely(lane < 0))
199 return serdes_get_bank_by_lane(lane);
202 static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
207 for (lane = first; lane < SRDS_MAX_LANES; lane++) {
208 if (serdes_get_prtcl(prtcl, lane) != device)
215 static void __serdes_reset_rx(serdes_corenet_t *regs,
217 enum srds_prtcl device)
219 int lane, idx, first, last;
221 lane = __serdes_get_first_lane(prtcl, device);
222 if (unlikely(lane < 0))
224 first = serdes_get_lane_idx(lane);
225 last = first + __serdes_get_lane_count(prtcl, device, lane);
228 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
229 * selected as XAUI to place the lane into reset.
231 for (idx = first; idx < last; idx++)
232 clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
234 /* Wait at least 250 ns */
238 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
239 * selected as XAUI to bring the lane out of reset.
241 for (idx = first; idx < last; idx++)
242 setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
245 void serdes_reset_rx(enum srds_prtcl device)
248 const ccsr_gur_t *gur;
249 serdes_corenet_t *regs;
251 if (unlikely(device == NONE))
254 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
256 /* Is serdes enabled at all? */
257 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
260 regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
261 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
263 __serdes_reset_rx(regs, prtcl, device);
267 #ifndef CONFIG_SYS_DCSRBAR_PHYS
268 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
269 #define CONFIG_SYS_DCSRBAR 0x80000000
270 #define __DCSR_NOT_DEFINED_BY_CONFIG
273 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
275 * Enable a SERDES bank that was disabled via the RCW
277 * We only call this function for SERDES8 and SERDES-A001 in cases we really
278 * want to enable the bank, whether we actually want to use the lanes or not,
279 * so make sure at least one lane is enabled. We're only enabling this one
280 * lane to satisfy errata requirements that the bank be enabled.
282 * We use a local variable instead of srds_lpd_b[] because we want drivers to
283 * think that the lanes actually are disabled.
285 static void enable_bank(ccsr_gur_t *gur, int bank)
288 u32 temp_lpd_b = srds_lpd_b[bank];
291 * If we're asked to disable all lanes, just pretend we're doing
294 if (temp_lpd_b == 0xF)
298 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
299 * CCSR, and read/write in DSCR.
301 rcw5 = in_be32(gur->rcwsr + 5);
302 if (bank == FSL_SRDS_BANK_2) {
303 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
304 rcw5 |= temp_lpd_b << 26;
305 } else if (bank == FSL_SRDS_BANK_3) {
306 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
307 rcw5 |= temp_lpd_b << 18;
309 printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
313 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
314 * of the DCSR mapping.
317 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
318 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
321 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
322 LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
324 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
327 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
329 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
331 disable_law(law_index);
333 set_law(law.index, law.addr, law.size, law.trgt_id);
339 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
340 * bank 3 to clock banks 2 and 3, as well as a limited selection of
341 * protocol configurations. This requires that banks 2 and 3's lanes be
342 * disabled in the RCW, and enabled with some fixup here to re-enable
343 * them, and to configure bank 2's clock parameters in bank 3's pll in
344 * cases where they differ.
346 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
347 u32 devdisr, u32 devdisr2, int cfg)
353 * The disabled lanes of bank 2 will cause the associated
354 * logic blocks to be disabled in DEVDISR. We reverse that here.
356 * Note that normally it is not permitted to clear DEVDISR bits
357 * once the device has been disabled, but the hardware people
358 * say that this special case is OK.
360 clrbits_be32(&gur->devdisr, devdisr);
361 clrbits_be32(&gur->devdisr2, devdisr2);
364 * Some protocols require special handling. There are a few
365 * additional protocol configurations that can be used, which are
366 * not listed here. See app note 4065 for supported protocol
372 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
373 * SGMII on bank 3 should still be usable.
375 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
376 SRDS_PLLCR1_PLL_BWSEL);
382 * Banks 2 (XAUI) and 3 (SGMII) have different clocking
383 * requirements in these configurations. Bank 3 cannot
384 * be used and should have its lanes (but not the bank
385 * itself) disabled in the RCW. We set up bank 3's pll
386 * for bank 2's needs here.
388 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
390 /* Determine refclock from XAUI ratio */
391 switch (srds_ratio_b2) {
393 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
396 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
399 printf("SERDES: bad SRDS_RATIO_B2 %d\n",
404 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
405 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
407 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
408 SRDS_PLLCR0_FRATE_SEL_MASK,
409 SRDS_PLLCR0_FRATE_SEL_6_25);
413 enable_bank(gur, FSL_SRDS_BANK_3);
417 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
419 * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
420 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
422 static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
424 enum srds_prtcl device;
430 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
433 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
434 SRDS_PLLCR1_PLL_BWSEL);
438 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
439 * SRDSB3PLLCR1[PLLBW_SEL] to 1.
441 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
442 SRDS_PLLCR1_PLL_BWSEL);
443 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
444 SRDS_PLLCR1_PLL_BWSEL);
449 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
450 * before XAUI is initialized.
452 for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
453 if (is_serdes_configured(device)) {
454 int bank = serdes_get_bank_by_device(cfg, device);
456 clrbits_be32(®s->bank[bank].pllcr1,
457 SRDS_PLLCR1_PLL_BWSEL);
464 * Wait for the RSTDONE bit to get set, or a one-second timeout.
466 static void wait_for_rstdone(unsigned int bank)
468 serdes_corenet_t *srds_regs =
469 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
470 unsigned long long end_tick;
473 /* wait for reset complete or 1-second timeout */
474 end_tick = usec2ticks(1000000) + get_ticks();
476 rstctl = in_be32(&srds_regs->bank[bank].rstctl);
477 if (rstctl & SRDS_RSTCTL_RSTDONE)
479 } while (end_tick > get_ticks());
481 if (!(rstctl & SRDS_RSTCTL_RSTDONE))
482 printf("SERDES: timeout resetting bank %u\n", bank + 1);
486 void __soc_serdes_init(void)
488 /* Allow for SoC-specific initialization in <SOC>_serdes.c */
490 void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
492 void fsl_serdes_init(void)
494 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
496 serdes_corenet_t *srds_regs;
498 enum srds_prtcl lane_prtcl;
499 int have_bank[SRDS_MAX_BANK] = {};
500 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
501 u32 serdes8_devdisr = 0;
502 u32 serdes8_devdisr2 = 0;
503 char srds_lpd_opt[16];
504 const char *srds_lpd_arg;
507 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
508 enum srds_prtcl device;
510 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
511 int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */
513 char buffer[HWCONFIG_BUFFER_SIZE];
517 * Extract hwconfig from environment since we have not properly setup
518 * the environment but need it for ddr config params
520 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
523 /* Is serdes enabled at all? */
524 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
527 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
528 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
529 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
531 if (!is_serdes_prtcl_valid(cfg)) {
532 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
536 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
538 * Display a warning if banks two and three are not disabled in the RCW,
539 * since our work-around for SERDES8 depends on these banks being
540 * disabled at power-on.
542 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
543 if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) {
544 printf("Warning: SERDES8 requires banks two and "
545 "three to be disabled in the RCW\n");
549 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
550 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
551 * for a description of these options.
553 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
554 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
556 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
559 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
562 if ((cfg == 0xf) || (cfg == 0x10)) {
564 * For SERDES protocols 0xF and 0x10, force bank 3 to be
565 * disabled, because it is not supported.
567 srds_lpd_b[FSL_SRDS_BANK_3] = 0xF;
571 /* Look for banks with all lanes disabled, and power down the bank. */
572 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
573 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
574 if (serdes_lane_enabled(lane)) {
575 have_bank[serdes_get_bank_by_lane(lane)] = 1;
576 serdes_prtcl_map |= (1 << lane_prtcl);
582 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
584 * Bank two uses the clock from bank three, so if bank two is enabled,
585 * then bank three must also be enabled.
587 if (have_bank[FSL_SRDS_BANK_2])
588 have_bank[FSL_SRDS_BANK_3] = 1;
591 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
593 * The work-aroud for erratum SERDES-A001 is needed only if bank two
594 * is disabled and bank three is enabled. The converse is also true,
595 * but SERDES8 ensures that bank 3 is always enabled if bank 2 is
596 * enabled, so there's no point in complicating the code to handle
600 !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3];
603 /* Power down the banks we're not interested in */
604 for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
605 if (!have_bank[bank]) {
606 printf("SERDES: bank %d disabled\n", bank + 1);
607 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
609 * Erratum SERDES-A001 says bank two needs to be powered
610 * down after bank three is powered up, so don't power
611 * down bank two here.
613 if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2))
614 setbits_be32(&srds_regs->bank[bank].rstctl,
617 setbits_be32(&srds_regs->bank[bank].rstctl,
623 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
624 idx = serdes_get_lane_idx(lane);
625 lane_prtcl = serdes_get_prtcl(cfg, lane);
642 printf("%s ", serdes_prtcl_str[lane_prtcl]);
645 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
647 * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
648 * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
649 * AURORA before the device is initialized.
651 switch (lane_prtcl) {
652 case SGMII_FM1_DTSEC1:
653 case SGMII_FM1_DTSEC2:
654 case SGMII_FM1_DTSEC3:
655 case SGMII_FM1_DTSEC4:
656 case SGMII_FM2_DTSEC1:
657 case SGMII_FM2_DTSEC2:
658 case SGMII_FM2_DTSEC3:
659 case SGMII_FM2_DTSEC4:
665 clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
666 SRDS_TTLCR0_FLT_SEL_MASK,
667 SRDS_TTLCR0_FLT_SEL_750PPM |
674 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
675 switch (lane_prtcl) {
679 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
680 (lane_prtcl - PCIE1);
684 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
685 (lane_prtcl - SRIO1);
687 case SGMII_FM1_DTSEC1:
688 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
689 FSL_CORENET_DEVDISR2_DTSEC1_1;
691 case SGMII_FM1_DTSEC2:
692 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
693 FSL_CORENET_DEVDISR2_DTSEC1_2;
695 case SGMII_FM1_DTSEC3:
696 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
697 FSL_CORENET_DEVDISR2_DTSEC1_3;
699 case SGMII_FM1_DTSEC4:
700 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
701 FSL_CORENET_DEVDISR2_DTSEC1_4;
703 case SGMII_FM2_DTSEC1:
704 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
705 FSL_CORENET_DEVDISR2_DTSEC2_1;
707 case SGMII_FM2_DTSEC2:
708 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
709 FSL_CORENET_DEVDISR2_DTSEC2_2;
711 case SGMII_FM2_DTSEC3:
712 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
713 FSL_CORENET_DEVDISR2_DTSEC2_3;
715 case SGMII_FM2_DTSEC4:
716 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
717 FSL_CORENET_DEVDISR2_DTSEC2_4;
720 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
721 FSL_CORENET_DEVDISR2_10GEC1;
724 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
725 FSL_CORENET_DEVDISR2_10GEC2;
740 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
741 p4080_erratum_serdes_a005(srds_regs, cfg);
744 for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
747 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
749 * Change bank init order to 0, 2, 1, so that the third bank's
750 * PLL is established before we start the second bank. The
751 * second bank uses the third bank's PLL.
755 bank = FSL_SRDS_BANK_3;
757 bank = FSL_SRDS_BANK_2;
760 /* Skip disabled banks */
761 if (!have_bank[bank])
764 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
767 * Re-enable devices on banks two and three that were
768 * disabled by the RCW, and then enable bank three. The
769 * devices need to be enabled before either bank is
772 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
773 serdes8_devdisr2, cfg);
774 } else if (idx == 2) {
775 /* Enable bank two now that bank three is enabled. */
776 enable_bank(gur, FSL_SRDS_BANK_2);
780 wait_for_rstdone(bank);
783 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
784 if (need_serdes_a001) {
785 /* Bank 3 has been enabled, so now we can disable bank 2 */
786 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl,
791 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
792 for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
793 if (is_serdes_configured(device))
794 __serdes_reset_rx(srds_regs, cfg, device);