2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
11 #include <asm/fsl_serdes.h>
12 #include <asm/immap_85xx.h>
14 #include <asm/processor.h>
15 #include <asm/fsl_law.h>
16 #include <asm/errno.h>
17 #include "fsl_corenet_serdes.h"
20 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
21 * The code is already very complicated as it is, and separating the two
22 * completely would just make things worse. We try to keep them as separate
23 * as possible, but for now we require SERDES8 if SERDES_A001 is defined.
25 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
26 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
27 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
31 static u32 serdes_prtcl_map;
34 static const char *serdes_prtcl_str[] = {
44 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
45 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
46 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
47 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
48 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
49 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
50 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
51 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
52 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
53 [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
54 [XAUI_FM1] = "XAUI_FM1",
55 [XAUI_FM2] = "XAUI_FM2",
62 unsigned int lpd; /* RCW lane powerdown bit */
64 } lanes[SRDS_MAX_LANES] = {
65 { 0, 152, FSL_SRDS_BANK_1 },
66 { 1, 153, FSL_SRDS_BANK_1 },
67 { 2, 154, FSL_SRDS_BANK_1 },
68 { 3, 155, FSL_SRDS_BANK_1 },
69 { 4, 156, FSL_SRDS_BANK_1 },
70 { 5, 157, FSL_SRDS_BANK_1 },
71 { 6, 158, FSL_SRDS_BANK_1 },
72 { 7, 159, FSL_SRDS_BANK_1 },
73 { 8, 160, FSL_SRDS_BANK_1 },
74 { 9, 161, FSL_SRDS_BANK_1 },
75 { 16, 162, FSL_SRDS_BANK_2 },
76 { 17, 163, FSL_SRDS_BANK_2 },
77 { 18, 164, FSL_SRDS_BANK_2 },
78 { 19, 165, FSL_SRDS_BANK_2 },
79 #ifdef CONFIG_PPC_P4080
80 { 20, 170, FSL_SRDS_BANK_3 },
81 { 21, 171, FSL_SRDS_BANK_3 },
82 { 22, 172, FSL_SRDS_BANK_3 },
83 { 23, 173, FSL_SRDS_BANK_3 },
85 { 20, 166, FSL_SRDS_BANK_3 },
86 { 21, 167, FSL_SRDS_BANK_3 },
87 { 22, 168, FSL_SRDS_BANK_3 },
88 { 23, 169, FSL_SRDS_BANK_3 },
91 { 24, 175, FSL_SRDS_BANK_4 },
92 { 25, 176, FSL_SRDS_BANK_4 },
96 int serdes_get_lane_idx(int lane)
98 return lanes[lane].idx;
101 int serdes_get_bank_by_lane(int lane)
103 return lanes[lane].bank;
106 int serdes_lane_enabled(int lane)
108 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
109 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
111 int bank = lanes[lane].bank;
112 int word = lanes[lane].lpd / 32;
113 int bit = lanes[lane].lpd % 32;
115 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
118 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
120 * For banks two and three, use the srds_lpd_b[] array instead of the
121 * RCW, because this array contains the real values of SRDS_LPD_B2 and
125 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
128 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
131 int is_serdes_configured(enum srds_prtcl device)
133 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
135 /* Is serdes enabled at all? */
136 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
139 return (1 << device) & serdes_prtcl_map;
142 static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
146 for (i = 0; i < SRDS_MAX_LANES; i++) {
147 if (serdes_get_prtcl(prtcl, i) == device)
155 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
156 * device. This depends on the current SERDES protocol, as defined in the RCW.
158 * Returns a negative error code if SERDES is disabled or the given device is
159 * not supported in the current SERDES protocol.
161 int serdes_get_first_lane(enum srds_prtcl device)
164 const ccsr_gur_t *gur;
166 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
168 /* Is serdes enabled at all? */
169 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
172 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
174 return __serdes_get_first_lane(prtcl, device);
177 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
179 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
182 * Returns a negative error code if the given device is not supported for the
183 * given SERDES protocol.
185 static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
189 lane = __serdes_get_first_lane(prtcl, device);
190 if (unlikely(lane < 0))
193 return serdes_get_bank_by_lane(lane);
196 static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
201 for (lane = first; lane < SRDS_MAX_LANES; lane++) {
202 if (serdes_get_prtcl(prtcl, lane) != device)
209 static void __serdes_reset_rx(serdes_corenet_t *regs,
211 enum srds_prtcl device)
213 int lane, idx, first, last;
215 lane = __serdes_get_first_lane(prtcl, device);
216 if (unlikely(lane < 0))
218 first = serdes_get_lane_idx(lane);
219 last = first + __serdes_get_lane_count(prtcl, device, lane);
222 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
223 * selected as XAUI to place the lane into reset.
225 for (idx = first; idx < last; idx++)
226 clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
228 /* Wait at least 250 ns */
232 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
233 * selected as XAUI to bring the lane out of reset.
235 for (idx = first; idx < last; idx++)
236 setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
239 void serdes_reset_rx(enum srds_prtcl device)
242 const ccsr_gur_t *gur;
243 serdes_corenet_t *regs;
245 if (unlikely(device == NONE))
248 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
250 /* Is serdes enabled at all? */
251 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
254 regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
255 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
257 __serdes_reset_rx(regs, prtcl, device);
261 #ifndef CONFIG_SYS_DCSRBAR_PHYS
262 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
263 #define CONFIG_SYS_DCSRBAR 0x80000000
264 #define __DCSR_NOT_DEFINED_BY_CONFIG
267 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
269 * Enable a SERDES bank that was disabled via the RCW
271 * We only call this function for SERDES8 and SERDES-A001 in cases we really
272 * want to enable the bank, whether we actually want to use the lanes or not,
273 * so make sure at least one lane is enabled. We're only enabling this one
274 * lane to satisfy errata requirements that the bank be enabled.
276 * We use a local variable instead of srds_lpd_b[] because we want drivers to
277 * think that the lanes actually are disabled.
279 static void enable_bank(ccsr_gur_t *gur, int bank)
282 u32 temp_lpd_b = srds_lpd_b[bank];
285 * If we're asked to disable all lanes, just pretend we're doing
288 if (temp_lpd_b == 0xF)
292 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
293 * CCSR, and read/write in DSCR.
295 rcw5 = in_be32(gur->rcwsr + 5);
296 if (bank == FSL_SRDS_BANK_2) {
297 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
298 rcw5 |= temp_lpd_b << 26;
299 } else if (bank == FSL_SRDS_BANK_3) {
300 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
301 rcw5 |= temp_lpd_b << 18;
303 printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
307 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
308 * of the DCSR mapping.
311 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
312 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
315 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
316 LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
318 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
321 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
323 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
325 disable_law(law_index);
327 set_law(law.index, law.addr, law.size, law.trgt_id);
333 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
334 * bank 3 to clock banks 2 and 3, as well as a limited selection of
335 * protocol configurations. This requires that banks 2 and 3's lanes be
336 * disabled in the RCW, and enabled with some fixup here to re-enable
337 * them, and to configure bank 2's clock parameters in bank 3's pll in
338 * cases where they differ.
340 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
341 u32 devdisr, u32 devdisr2, int cfg)
347 * The disabled lanes of bank 2 will cause the associated
348 * logic blocks to be disabled in DEVDISR. We reverse that here.
350 * Note that normally it is not permitted to clear DEVDISR bits
351 * once the device has been disabled, but the hardware people
352 * say that this special case is OK.
354 clrbits_be32(&gur->devdisr, devdisr);
355 clrbits_be32(&gur->devdisr2, devdisr2);
358 * Some protocols require special handling. There are a few
359 * additional protocol configurations that can be used, which are
360 * not listed here. See app note 4065 for supported protocol
366 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
367 * SGMII on bank 3 should still be usable.
369 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
370 SRDS_PLLCR1_PLL_BWSEL);
376 * Banks 2 (XAUI) and 3 (SGMII) have different clocking
377 * requirements in these configurations. Bank 3 cannot
378 * be used and should have its lanes (but not the bank
379 * itself) disabled in the RCW. We set up bank 3's pll
380 * for bank 2's needs here.
382 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
384 /* Determine refclock from XAUI ratio */
385 switch (srds_ratio_b2) {
387 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
390 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
393 printf("SERDES: bad SRDS_RATIO_B2 %d\n",
398 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
399 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
401 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
402 SRDS_PLLCR0_FRATE_SEL_MASK,
403 SRDS_PLLCR0_FRATE_SEL_6_25);
407 enable_bank(gur, FSL_SRDS_BANK_3);
411 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
413 * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
414 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
416 static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
418 enum srds_prtcl device;
424 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
427 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
428 SRDS_PLLCR1_PLL_BWSEL);
432 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
433 * SRDSB3PLLCR1[PLLBW_SEL] to 1.
435 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
436 SRDS_PLLCR1_PLL_BWSEL);
437 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
438 SRDS_PLLCR1_PLL_BWSEL);
443 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
444 * before XAUI is initialized.
446 for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
447 if (is_serdes_configured(device)) {
448 int bank = serdes_get_bank_by_device(cfg, device);
450 clrbits_be32(®s->bank[bank].pllcr1,
451 SRDS_PLLCR1_PLL_BWSEL);
458 * Wait for the RSTDONE bit to get set, or a one-second timeout.
460 static void wait_for_rstdone(unsigned int bank)
462 serdes_corenet_t *srds_regs =
463 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
464 unsigned long long end_tick;
467 /* wait for reset complete or 1-second timeout */
468 end_tick = usec2ticks(1000000) + get_ticks();
470 rstctl = in_be32(&srds_regs->bank[bank].rstctl);
471 if (rstctl & SRDS_RSTCTL_RSTDONE)
473 } while (end_tick > get_ticks());
475 if (!(rstctl & SRDS_RSTCTL_RSTDONE))
476 printf("SERDES: timeout resetting bank %u\n", bank + 1);
480 static void __soc_serdes_init(void)
482 /* Allow for SoC-specific initialization in <SOC>_serdes.c */
484 void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
486 void fsl_serdes_init(void)
488 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
490 serdes_corenet_t *srds_regs;
491 #ifdef CONFIG_PPC_P5040
492 serdes_corenet_t *srds2_regs;
495 int have_bank[SRDS_MAX_BANK] = {};
496 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
497 u32 serdes8_devdisr = 0;
498 u32 serdes8_devdisr2 = 0;
499 char srds_lpd_opt[16];
500 const char *srds_lpd_arg;
503 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
504 int need_serdes_a001; /* true == need work-around for SERDES A001 */
506 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
507 char buffer[HWCONFIG_BUFFER_SIZE];
511 * Extract hwconfig from environment since we have not properly setup
512 * the environment but need it for ddr config params
514 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
518 /* Is serdes enabled at all? */
519 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
522 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
523 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
524 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
526 if (!is_serdes_prtcl_valid(cfg)) {
527 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
531 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
533 * Display a warning if banks two and three are not disabled in the RCW,
534 * since our work-around for SERDES8 depends on these banks being
535 * disabled at power-on.
537 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
538 if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) {
539 printf("Warning: SERDES8 requires banks two and "
540 "three to be disabled in the RCW\n");
544 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
545 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
546 * for a description of these options.
548 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
549 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
551 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
554 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
557 if ((cfg == 0xf) || (cfg == 0x10)) {
559 * For SERDES protocols 0xF and 0x10, force bank 3 to be
560 * disabled, because it is not supported.
562 srds_lpd_b[FSL_SRDS_BANK_3] = 0xF;
566 /* Look for banks with all lanes disabled, and power down the bank. */
567 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
568 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
569 if (serdes_lane_enabled(lane)) {
570 have_bank[serdes_get_bank_by_lane(lane)] = 1;
571 serdes_prtcl_map |= (1 << lane_prtcl);
575 #ifdef CONFIG_PPC_P5040
577 * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
578 * protocols, these lanes are routed to SATA. We use serdes_prtcl_map
579 * to decide whether a protocol is supported on a given lane, so SATA
580 * will be identified as not supported, and therefore not initialized.
581 * So for protocols which use SATA on bank4, we add SATA support in
593 serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
596 srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
598 /* We don't need bank 4, so power it down */
599 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
605 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
607 * Bank two uses the clock from bank three, so if bank two is enabled,
608 * then bank three must also be enabled.
610 if (have_bank[FSL_SRDS_BANK_2])
611 have_bank[FSL_SRDS_BANK_3] = 1;
614 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
616 * The work-aroud for erratum SERDES-A001 is needed only if bank two
617 * is disabled and bank three is enabled. The converse is also true,
618 * but SERDES8 ensures that bank 3 is always enabled if bank 2 is
619 * enabled, so there's no point in complicating the code to handle
623 !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3];
626 /* Power down the banks we're not interested in */
627 for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
628 if (!have_bank[bank]) {
629 printf("SERDES: bank %d disabled\n", bank + 1);
630 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
632 * Erratum SERDES-A001 says bank two needs to be powered
633 * down after bank three is powered up, so don't power
634 * down bank two here.
636 if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2))
637 setbits_be32(&srds_regs->bank[bank].rstctl,
640 setbits_be32(&srds_regs->bank[bank].rstctl,
646 #ifdef CONFIG_SYS_FSL_ERRATUM_A004699
648 * To avoid the situation that resulted in the P4080 erratum
649 * SERDES-8, a given SerDes bank will use the PLLs from the previous
650 * bank if one of the PLL frequencies is a multiple of the other. For
651 * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
652 * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says
653 * that, in this situation, lane synchronization is not initiated. So
654 * when we detect a bank with a "borrowed" PLL, we have to manually
655 * initiate lane synchronization.
657 for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
658 /* Determine the first lane for this bank */
661 for (lane = 0; lane < SRDS_MAX_LANES; lane++)
662 if (lanes[lane].bank == bank)
664 idx = lanes[lane].idx;
667 * Check if the PLL for the bank is borrowed. The UOTHL
668 * bit of the first lane will tell us that.
670 if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
671 /* Manually start lane synchronization */
672 setbits_be32(&srds_regs->bank[bank].pllcr0,
673 SRDS_PLLCR0_PVCOCNT_EN);
678 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
679 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
680 enum srds_prtcl lane_prtcl;
682 idx = serdes_get_lane_idx(lane);
683 lane_prtcl = serdes_get_prtcl(cfg, lane);
700 printf("%s ", serdes_prtcl_str[lane_prtcl]);
703 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
705 * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
706 * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
707 * or AURORA before the device is initialized.
709 * Note that this part of the SERDES-9 work-around is
710 * redundant if the work-around for A-4580 has already been
713 switch (lane_prtcl) {
714 case SGMII_FM1_DTSEC1:
715 case SGMII_FM1_DTSEC2:
716 case SGMII_FM1_DTSEC3:
717 case SGMII_FM1_DTSEC4:
718 case SGMII_FM2_DTSEC1:
719 case SGMII_FM2_DTSEC2:
720 case SGMII_FM2_DTSEC3:
721 case SGMII_FM2_DTSEC4:
722 case SGMII_FM2_DTSEC5:
728 out_be32(&srds_regs->lane[idx].ttlcr0,
729 SRDS_TTLCR0_FLT_SEL_KFR_26 |
730 SRDS_TTLCR0_FLT_SEL_KPH_28 |
731 SRDS_TTLCR0_FLT_SEL_750PPM |
732 SRDS_TTLCR0_FREQOVD_EN);
739 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
740 switch (lane_prtcl) {
744 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
745 (lane_prtcl - PCIE1);
749 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
750 (lane_prtcl - SRIO1);
752 case SGMII_FM1_DTSEC1:
753 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
754 FSL_CORENET_DEVDISR2_DTSEC1_1;
756 case SGMII_FM1_DTSEC2:
757 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
758 FSL_CORENET_DEVDISR2_DTSEC1_2;
760 case SGMII_FM1_DTSEC3:
761 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
762 FSL_CORENET_DEVDISR2_DTSEC1_3;
764 case SGMII_FM1_DTSEC4:
765 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
766 FSL_CORENET_DEVDISR2_DTSEC1_4;
768 case SGMII_FM2_DTSEC1:
769 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
770 FSL_CORENET_DEVDISR2_DTSEC2_1;
772 case SGMII_FM2_DTSEC2:
773 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
774 FSL_CORENET_DEVDISR2_DTSEC2_2;
776 case SGMII_FM2_DTSEC3:
777 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
778 FSL_CORENET_DEVDISR2_DTSEC2_3;
780 case SGMII_FM2_DTSEC4:
781 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
782 FSL_CORENET_DEVDISR2_DTSEC2_4;
784 case SGMII_FM2_DTSEC5:
785 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
786 FSL_CORENET_DEVDISR2_DTSEC2_5;
789 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
790 FSL_CORENET_DEVDISR2_10GEC1;
793 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
794 FSL_CORENET_DEVDISR2_10GEC2;
810 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
811 p4080_erratum_serdes_a005(srds_regs, cfg);
814 for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
817 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
819 * Change bank init order to 0, 2, 1, so that the third bank's
820 * PLL is established before we start the second bank. The
821 * second bank uses the third bank's PLL.
825 bank = FSL_SRDS_BANK_3;
827 bank = FSL_SRDS_BANK_2;
830 /* Skip disabled banks */
831 if (!have_bank[bank])
834 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
837 * Re-enable devices on banks two and three that were
838 * disabled by the RCW, and then enable bank three. The
839 * devices need to be enabled before either bank is
842 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
843 serdes8_devdisr2, cfg);
844 } else if (idx == 2) {
845 /* Enable bank two now that bank three is enabled. */
846 enable_bank(gur, FSL_SRDS_BANK_2);
850 wait_for_rstdone(bank);
853 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
854 if (need_serdes_a001) {
855 /* Bank 3 has been enabled, so now we can disable bank 2 */
856 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl,
862 const char *serdes_clock_to_string(u32 clock)
865 case SRDS_PLLCR0_RFCK_SEL_100:
867 case SRDS_PLLCR0_RFCK_SEL_125:
869 case SRDS_PLLCR0_RFCK_SEL_156_25:
871 case SRDS_PLLCR0_RFCK_SEL_161_13:
872 return "161.1328123";