2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
27 #include <asm/fsl_serdes.h>
28 #include <asm/immap_85xx.h>
30 #include <asm/processor.h>
31 #include <asm/fsl_law.h>
32 #include <asm/errno.h>
33 #include "fsl_corenet_serdes.h"
35 static u32 serdes_prtcl_map;
37 #define HWCONFIG_BUFFER_SIZE 128
40 static const char *serdes_prtcl_str[] = {
50 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
51 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
52 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
53 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
54 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
55 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
56 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
57 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
58 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
59 [XAUI_FM1] = "XAUI_FM1",
60 [XAUI_FM2] = "XAUI_FM2",
67 unsigned int lpd; /* RCW lane powerdown bit */
69 } lanes[SRDS_MAX_LANES] = {
70 { 0, 152, FSL_SRDS_BANK_1 },
71 { 1, 153, FSL_SRDS_BANK_1 },
72 { 2, 154, FSL_SRDS_BANK_1 },
73 { 3, 155, FSL_SRDS_BANK_1 },
74 { 4, 156, FSL_SRDS_BANK_1 },
75 { 5, 157, FSL_SRDS_BANK_1 },
76 { 6, 158, FSL_SRDS_BANK_1 },
77 { 7, 159, FSL_SRDS_BANK_1 },
78 { 8, 160, FSL_SRDS_BANK_1 },
79 { 9, 161, FSL_SRDS_BANK_1 },
80 { 16, 162, FSL_SRDS_BANK_2 },
81 { 17, 163, FSL_SRDS_BANK_2 },
82 { 18, 164, FSL_SRDS_BANK_2 },
83 { 19, 165, FSL_SRDS_BANK_2 },
84 { 20, 170, FSL_SRDS_BANK_3 },
85 { 21, 171, FSL_SRDS_BANK_3 },
86 { 22, 172, FSL_SRDS_BANK_3 },
87 { 23, 173, FSL_SRDS_BANK_3 },
90 int serdes_get_lane_idx(int lane)
92 return lanes[lane].idx;
95 int serdes_get_bank_by_lane(int lane)
97 return lanes[lane].bank;
100 int serdes_lane_enabled(int lane)
102 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
103 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
105 int bank = lanes[lane].bank;
106 int word = lanes[lane].lpd / 32;
107 int bit = lanes[lane].lpd % 32;
109 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
112 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
114 * For banks two and three, use the srds_lpd_b[] array instead of the
115 * RCW, because this array contains the real values of SRDS_LPD_B2 and
119 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
122 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
125 int is_serdes_configured(enum srds_prtcl device)
127 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
129 /* Is serdes enabled at all? */
130 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
133 return (1 << device) & serdes_prtcl_map;
136 static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
140 for (i = 0; i < SRDS_MAX_LANES; i++) {
141 if (serdes_get_prtcl(prtcl, i) == device)
149 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
150 * device. This depends on the current SERDES protocol, as defined in the RCW.
152 * Returns a negative error code if SERDES is disabled or the given device is
153 * not supported in the current SERDES protocol.
155 int serdes_get_first_lane(enum srds_prtcl device)
158 const ccsr_gur_t *gur;
160 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
162 /* Is serdes enabled at all? */
163 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
166 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
168 return __serdes_get_first_lane(prtcl, device);
171 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
173 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
176 * Returns a negative error code if the given device is not supported for the
177 * given SERDES protocol.
179 static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
183 lane = __serdes_get_first_lane(prtcl, device);
184 if (unlikely(lane < 0))
187 return serdes_get_bank_by_lane(lane);
190 static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
195 for (lane = first; lane < SRDS_MAX_LANES; lane++) {
196 if (serdes_get_prtcl(prtcl, lane) != device)
203 static void __serdes_reset_rx(serdes_corenet_t *regs,
205 enum srds_prtcl device)
207 int lane, idx, first, last;
209 lane = __serdes_get_first_lane(prtcl, device);
210 if (unlikely(lane < 0))
212 first = serdes_get_lane_idx(lane);
213 last = first + __serdes_get_lane_count(prtcl, device, lane);
216 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
217 * selected as XAUI to place the lane into reset.
219 for (idx = first; idx < last; idx++)
220 clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
222 /* Wait at least 250 ns */
226 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
227 * selected as XAUI to bring the lane out of reset.
229 for (idx = first; idx < last; idx++)
230 setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
233 void serdes_reset_rx(enum srds_prtcl device)
236 const ccsr_gur_t *gur;
237 serdes_corenet_t *regs;
239 if (unlikely(device == NONE))
242 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
244 /* Is serdes enabled at all? */
245 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
248 regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
249 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
251 __serdes_reset_rx(regs, prtcl, device);
255 #ifndef CONFIG_SYS_DCSRBAR_PHYS
256 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
257 #define CONFIG_SYS_DCSRBAR 0x80000000
258 #define __DCSR_NOT_DEFINED_BY_CONFIG
261 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
262 static void enable_bank(ccsr_gur_t *gur, int bank)
267 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
268 * CCSR, and read/write in DSCR.
270 rcw5 = in_be32(gur->rcwsr + 5);
271 if (bank == FSL_SRDS_BANK_2) {
272 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
273 rcw5 |= srds_lpd_b[bank] << 26;
274 } else if (bank == FSL_SRDS_BANK_3) {
275 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
276 rcw5 |= srds_lpd_b[bank] << 18;
278 printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
282 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
283 * of the DCSR mapping.
286 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
287 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
290 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
291 LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
293 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
296 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
298 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
300 disable_law(law_index);
302 set_law(law.index, law.addr, law.size, law.trgt_id);
308 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
309 * bank 3 to clock banks 2 and 3, as well as a limited selection of
310 * protocol configurations. This requires that banks 2 and 3's lanes be
311 * disabled in the RCW, and enabled with some fixup here to re-enable
312 * them, and to configure bank 2's clock parameters in bank 3's pll in
313 * cases where they differ.
315 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
316 u32 devdisr, u32 devdisr2, int cfg)
322 * The disabled lanes of bank 2 will cause the associated
323 * logic blocks to be disabled in DEVDISR. We reverse that here.
325 * Note that normally it is not permitted to clear DEVDISR bits
326 * once the device has been disabled, but the hardware people
327 * say that this special case is OK.
329 clrbits_be32(&gur->devdisr, devdisr);
330 clrbits_be32(&gur->devdisr2, devdisr2);
333 * Some protocols require special handling. There are a few
334 * additional protocol configurations that can be used, which are
335 * not listed here. See app note 4065 for supported protocol
341 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
342 * SGMII on bank 3 should still be usable.
344 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
345 SRDS_PLLCR1_PLL_BWSEL);
347 enable_bank(gur, FSL_SRDS_BANK_3);
353 * Banks 2 (XAUI) and 3 (SGMII) have different clocking
354 * requirements in these configurations. Bank 3 cannot
355 * be used and should have its lanes (but not the bank
356 * itself) disabled in the RCW. We set up bank 3's pll
357 * for bank 2's needs here.
359 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
361 /* Determine refclock from XAUI ratio */
362 switch (srds_ratio_b2) {
364 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
367 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
370 printf("SERDES: bad SRDS_RATIO_B2 %d\n",
375 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
376 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
378 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
379 SRDS_PLLCR0_FRATE_SEL_MASK,
380 SRDS_PLLCR0_FRATE_SEL_6_25);
383 enable_bank(gur, FSL_SRDS_BANK_3);
389 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
391 * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
392 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
394 static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
396 enum srds_prtcl device;
402 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
405 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
406 SRDS_PLLCR1_PLL_BWSEL);
410 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
411 * SRDSB3PLLCR1[PLLBW_SEL] to 1.
413 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
414 SRDS_PLLCR1_PLL_BWSEL);
415 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
416 SRDS_PLLCR1_PLL_BWSEL);
421 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
422 * before XAUI is initialized.
424 for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
425 if (is_serdes_configured(device)) {
426 int bank = serdes_get_bank_by_device(cfg, device);
428 clrbits_be32(®s->bank[bank].pllcr1,
429 SRDS_PLLCR1_PLL_BWSEL);
435 void fsl_serdes_init(void)
437 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
439 serdes_corenet_t *srds_regs;
441 enum srds_prtcl lane_prtcl;
443 int have_bank[SRDS_MAX_BANK] = {};
444 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
445 u32 serdes8_devdisr = 0;
446 u32 serdes8_devdisr2 = 0;
447 char srds_lpd_opt[16];
448 const char *srds_lpd_arg;
451 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
452 enum srds_prtcl device;
454 char buffer[HWCONFIG_BUFFER_SIZE];
458 * Extract hwconfig from environment since we have not properly setup
459 * the environment but need it for ddr config params
461 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
464 /* Is serdes enabled at all? */
465 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
468 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
469 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
470 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
472 if (!is_serdes_prtcl_valid(cfg)) {
473 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
477 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
479 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
480 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
481 * for a description of these options.
483 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
484 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
486 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
489 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
493 /* Look for banks with all lanes disabled, and power down the bank. */
494 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
495 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
496 if (serdes_lane_enabled(lane)) {
497 have_bank[serdes_get_bank_by_lane(lane)] = 1;
498 serdes_prtcl_map |= (1 << lane_prtcl);
502 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
504 * Bank two uses the clock from bank three, so if bank two is enabled,
505 * then bank three must also be enabled.
507 if (have_bank[FSL_SRDS_BANK_2])
508 have_bank[FSL_SRDS_BANK_3] = 1;
511 for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
512 if (!have_bank[bank]) {
513 printf("SERDES: bank %d disabled\n", bank + 1);
514 setbits_be32(&srds_regs->bank[bank].rstctl,
519 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
520 idx = serdes_get_lane_idx(lane);
521 lane_prtcl = serdes_get_prtcl(cfg, lane);
538 printf("%s ", serdes_prtcl_str[lane_prtcl]);
541 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
542 switch (lane_prtcl) {
546 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
547 (lane_prtcl - PCIE1);
551 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
552 (lane_prtcl - SRIO1);
554 case SGMII_FM1_DTSEC1:
555 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
556 FSL_CORENET_DEVDISR2_DTSEC1_1;
558 case SGMII_FM1_DTSEC2:
559 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
560 FSL_CORENET_DEVDISR2_DTSEC1_2;
562 case SGMII_FM1_DTSEC3:
563 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
564 FSL_CORENET_DEVDISR2_DTSEC1_3;
566 case SGMII_FM1_DTSEC4:
567 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
568 FSL_CORENET_DEVDISR2_DTSEC1_4;
570 case SGMII_FM2_DTSEC1:
571 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
572 FSL_CORENET_DEVDISR2_DTSEC2_1;
574 case SGMII_FM2_DTSEC2:
575 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
576 FSL_CORENET_DEVDISR2_DTSEC2_2;
578 case SGMII_FM2_DTSEC3:
579 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
580 FSL_CORENET_DEVDISR2_DTSEC2_3;
582 case SGMII_FM2_DTSEC4:
583 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
584 FSL_CORENET_DEVDISR2_DTSEC2_4;
588 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
590 * Set BnTTLCRy0[FLT_SEL] = 000011 and set
591 * BnTTLCRy0[17] = 1 for each of the SerDes lanes
592 * selected as XAUI on each bank before XAUI is
595 clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
596 SRDS_TTLCR0_FLT_SEL_MASK,
597 0x03000000 | SRDS_TTLCR0_PM_DIS);
599 if (lane_prtcl == XAUI_FM1)
600 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
601 FSL_CORENET_DEVDISR2_10GEC1;
603 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
604 FSL_CORENET_DEVDISR2_10GEC2;
619 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
620 p4080_erratum_serdes_a005(srds_regs, cfg);
623 for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
628 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
630 * Change bank init order to 0, 2, 1, so that the third bank's
631 * PLL is established before we start the second bank. The
632 * second bank uses the third bank's PLL.
636 bank = FSL_SRDS_BANK_3;
638 bank = FSL_SRDS_BANK_2;
641 /* Skip disabled banks */
642 if (!have_bank[bank])
645 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
648 * Re-enable devices on banks two and three that were
649 * disabled by the RCW, and then enable bank three. The
650 * devices need to be enabled before either bank is
653 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
654 serdes8_devdisr2, cfg);
655 } else if (idx == 2) {
656 /* Eable bank two now that bank three is enabled. */
657 enable_bank(gur, FSL_SRDS_BANK_2);
661 /* reset banks for errata */
662 setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST);
664 /* wait for reset complete or 1-second timeout */
665 end_tick = usec2ticks(1000000) + get_ticks();
667 rstctl = in_be32(&srds_regs->bank[bank].rstctl);
668 if (rstctl & SRDS_RSTCTL_RSTDONE)
670 } while (end_tick > get_ticks());
672 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) {
673 printf("SERDES: timeout resetting bank %d\n",
679 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
680 for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
681 if (is_serdes_configured(device))
682 __serdes_reset_rx(srds_regs, cfg, device);