2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2002 (440 port)
6 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
8 * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
39 int interrupt_init_cpu(unsigned int *decrementer_count)
41 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
45 * The POST word is stored in the PIC's TFRR register which gets
46 * cleared when the PIC is reset. Save it off so we can restore it
49 ulong post_word = post_word_load();
52 out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
53 while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
55 out_be32(&pic->gcr, MPC85xx_PICGCR_M);
58 *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
60 /* PIE is same as DIE, dec interrupt enable */
61 mtspr(SPRN_TCR, TCR_PIE);
63 #ifdef CONFIG_INTERRUPTS
64 pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
65 debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
67 pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
68 debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
70 pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
71 debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
74 pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
75 debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
77 #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
78 pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
79 debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
82 pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
83 debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
86 pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
87 debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
90 pic->ctpr=0; /* 40080 clear current task priority register */
94 post_word_store(post_word);
100 /* Install and free a interrupt handler. Not implemented yet. */
103 irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
109 irq_free_handler(int vec)
114 void timer_interrupt_cpu(struct pt_regs *regs)
116 /* PIS is same as DIS, dec interrupt status */
117 mtspr(SPRN_TSR, TSR_PIS);
120 #if defined(CONFIG_CMD_IRQ)
121 /* irqinfo - print information about PCI devices,not implemented. */
122 int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])