2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/fsl_serdes.h>
26 #include <asm/processor.h>
28 #include "fsl_corenet_serdes.h"
30 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
31 [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
32 SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1,
33 SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2,
34 NONE, NONE, AURORA, AURORA},
35 [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3,
36 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4,
37 SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2,
38 SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA},
39 [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
40 AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
41 SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
42 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
43 [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
44 AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
45 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
46 [0x1c] = {NONE, NONE, SRIO1, SRIO2, NONE, NONE, NONE, NONE,
47 AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
48 SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
49 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
52 enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
54 if (!serdes_lane_enabled(lane))
57 return serdes_cfg_tbl[cfg][lane];
60 int is_serdes_prtcl_valid(u32 prtcl)
64 if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
67 for (i = 0; i < SRDS_MAX_LANES; i++) {
68 if (serdes_cfg_tbl[prtcl][i] != NONE)
75 void soc_serdes_init(void)
78 * On the P3060 the devdisr2 register does not correctly reflect
79 * the state of the MACs based on the RCW fields. So disable the MACs
80 * based on the srds_prtcl and ec1, ec2, ec3 fields
83 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
84 u32 devdisr2 = in_be32(&gur->devdisr2);
85 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
87 /* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */
89 if (!is_serdes_configured(SGMII_FM1_DTSEC3))
90 devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3;
92 if (!is_serdes_configured(SGMII_FM1_DTSEC4))
93 devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4;
95 if (!is_serdes_configured(SGMII_FM2_DTSEC1))
96 devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1;
98 if (!is_serdes_configured(SGMII_FM2_DTSEC2))
99 devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2;
101 if (!is_serdes_configured(SGMII_FM2_DTSEC3))
102 devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3;
104 if (!is_serdes_configured(SGMII_FM2_DTSEC4))
105 devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4;
107 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
108 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) {
109 devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2;
112 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
113 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) {
114 devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1;
117 out_be32(&gur->devdisr2, devdisr2);