2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
30 #include <ppc_asm.tmpl>
33 #include <asm/cache.h>
36 /* To boot secondary cpus, we need a place for them to start up.
37 * Normally, they start at 0xfffffffc, but that's usually the
38 * firmware, and we don't want to have to run the firmware again.
39 * Instead, the primary cpu will set the BPTR to point here to
40 * this page. We then set up the core, and head to
41 * start_secondary. Note that this means that the code below
42 * must never exceed 1023 instructions (the branch at the end
43 * would then be the 1024th).
45 .globl __secondary_start_page
47 __secondary_start_page:
48 /* First do some preliminary setup */
49 lis r3, HID0_EMCP@h /* enable machine check */
51 ori r3,r3,HID0_TBEN@l /* enable Timebase */
53 #ifdef CONFIG_PHYS_64BIT
54 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
59 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
62 cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
64 /* Set MBDD bit also */
65 ori r3, r3, HID1_MBDD@l
70 /* Enable branch prediction */
72 ori r3,r3,BUCSR_ENABLE@l
80 /* Enable/invalidate the I-Cache */
81 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
82 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
89 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
90 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
95 andi. r1,r3,L1CSR1_ICE@l
98 /* Enable/invalidate the D-Cache */
99 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
100 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
107 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
108 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
113 andi. r1,r3,L1CSR0_DCE@l
116 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
118 /* get our PIR to figure out our table entry */
119 lis r3,toreset(__spin_table)@h
120 ori r3,r3,toreset(__spin_table)@l
122 /* r10 has the base address for the entry */
125 rlwinm r4,r0,27,27,31
132 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
133 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
139 #ifdef CONFIG_BACKSIDE_L2_CACHE
140 /* Enable/invalidate the L2 cache */
142 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
143 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
150 #ifdef CONFIG_SYS_CACHE_STASHING
151 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
156 lis r3,CONFIG_SYS_INIT_L2CSR0@h
157 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
162 andis. r1,r3,L2CSR0_L2E@h
166 #define EPAPR_MAGIC (0x45504150)
167 #define ENTRY_ADDR_UPPER 0
168 #define ENTRY_ADDR_LOWER 4
169 #define ENTRY_R3_UPPER 8
170 #define ENTRY_R3_LOWER 12
171 #define ENTRY_RESV 16
173 #define ENTRY_R6_UPPER 24
174 #define ENTRY_R6_LOWER 28
175 #define ENTRY_SIZE 32
177 /* setup the entry */
180 stw r0,ENTRY_PIR(r10)
181 stw r3,ENTRY_ADDR_UPPER(r10)
182 stw r8,ENTRY_ADDR_LOWER(r10)
183 stw r3,ENTRY_R3_UPPER(r10)
184 stw r4,ENTRY_R3_LOWER(r10)
185 stw r3,ENTRY_R6_UPPER(r10)
186 stw r3,ENTRY_R6_LOWER(r10)
188 /* load r13 with the address of the 'bootpg' in SDRAM */
189 lis r13,toreset(__bootpg_addr)@h
190 ori r13,r13,toreset(__bootpg_addr)@l
193 /* setup mapping for AS = 1, and jump there */
194 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
196 lis r11,(MAS1_VALID|MAS1_IPROT)@h
197 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
199 oris r11,r13,(MAS2_I|MAS2_G)@h
200 ori r11,r13,(MAS2_I|MAS2_G)@l
202 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
203 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
210 * OR in 0xfff to create a mask of the bootpg SDRAM address. We use
211 * this mask to fixup the cpu spin table and the address that we want
212 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
213 * bootpg is at 0x7ffff000 in SDRAM.
221 ori r12,r13,MSR_IS|MSR_DS@l
227 /* spin waiting for addr */
229 lwz r4,ENTRY_ADDR_LOWER(r10)
234 /* setup IVORs to match fixed offsets */
235 #include "fixed_ivor.S"
237 /* get the upper bits of the addr */
238 lwz r11,ENTRY_ADDR_UPPER(r10)
240 /* setup branch addr */
243 /* mark the entry as released */
245 stw r8,ENTRY_ADDR_LOWER(r10)
247 /* mask by ~64M to setup our tlb we will jump to */
250 /* setup r3, r4, r5, r6, r7, r8, r9 */
251 lwz r3,ENTRY_R3_LOWER(r10)
254 lwz r6,ENTRY_R6_LOWER(r10)
255 lis r7,(64*1024*1024)@h
259 /* load up the pir */
260 lwz r0,ENTRY_PIR(r10)
263 stw r0,ENTRY_PIR(r10)
267 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
268 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
269 * second mapping that maps addr 1:1 for 64M, and then we jump to
272 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
274 lis r10,(MAS1_VALID|MAS1_IPROT)@h
275 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
277 /* WIMGE = 0b00000 for now */
279 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
281 #ifdef CONFIG_ENABLE_36BIT_PHYS
286 /* Now we have another mapping for this page, so we jump to that
293 * Allocate some space for the SDRAM address of the bootpg.
294 * This variable has to be in the boot page so that it can
295 * be accessed by secondary cores when they come out of reset.
301 .align L1_CACHE_SHIFT
304 .space CONFIG_MAX_CPUS*ENTRY_SIZE
306 /* Fill in the empty space. The actual reset vector is
307 * the last word of the page */
308 __secondary_start_code_end:
309 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
310 __secondary_reset_vector:
311 b __secondary_start_page