2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm-offsets.h>
29 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
31 #include <ppc_asm.tmpl>
34 #include <asm/cache.h>
37 /* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page. We then set up the core, and head to
42 * start_secondary. Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
46 .globl __secondary_start_page
48 __secondary_start_page:
49 /* First do some preliminary setup */
50 lis r3, HID0_EMCP@h /* enable machine check */
52 ori r3,r3,HID0_TBEN@l /* enable Timebase */
54 #ifdef CONFIG_PHYS_64BIT
55 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
60 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
63 cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
65 /* Set MBDD bit also */
66 ori r3, r3, HID1_MBDD@l
71 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
77 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
80 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
84 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
85 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
90 /* Not a supported revision affected by erratum */
93 1: /* Erratum says set bits 55:60 to 001001 */
104 /* Enable branch prediction */
105 lis r3,BUCSR_ENABLE@h
106 ori r3,r3,BUCSR_ENABLE@l
114 /* Enable/invalidate the I-Cache */
115 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
116 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
123 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
124 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
129 andi. r1,r3,L1CSR1_ICE@l
132 /* Enable/invalidate the D-Cache */
133 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
134 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
141 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
142 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
147 andi. r1,r3,L1CSR0_DCE@l
150 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
152 /* get our PIR to figure out our table entry */
153 lis r3,toreset(__spin_table_addr)@h
154 ori r3,r3,toreset(__spin_table_addr)@l
158 * r10 has the base address for the entry.
159 * we cannot access it yet before setting up a new TLB
162 #if defined(CONFIG_E6500)
164 * PIR definition for E6500
165 * 0-17 Reserved (logic 0s)
166 * 8-19 CHIP_ID, 2'b00 - SoC 1
167 * all others - reserved
168 * 20-24 CLUSTER_ID 5'b00000 - CCM 1
169 * all others - reserved
170 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
174 * 27-28 CORE_ID 2'b00 - core 0
178 * 29-31 THREAD_ID 3'b000 - thread 0
181 rlwinm r4,r0,29,25,31
182 #elif defined(CONFIG_E500MC)
183 rlwinm r4,r0,27,27,31
187 slwi r8,r4,6 /* spin table is padded to 64 byte */
193 * core 0 thread 0: pir reset value 0x00, new pir 0
194 * core 0 thread 1: pir reset value 0x01, new pir 1
195 * core 1 thread 0: pir reset value 0x08, new pir 2
196 * core 1 thread 1: pir reset value 0x09, new pir 3
197 * core 2 thread 0: pir reset value 0x10, new pir 4
198 * core 2 thread 1: pir reset value 0x11, new pir 5
201 * Only thread 0 of each core will be running, updating PIR doesn't
202 * need to deal with the thread bits.
204 rlwinm r4,r0,30,24,30
207 mtspr SPRN_PIR,r4 /* write to PIR register */
209 #ifdef CONFIG_SYS_CACHE_STASHING
210 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
216 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
217 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
219 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
220 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
221 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
224 rlwinm r6,r3,24,~0x800 /* clear E bit */
227 ori r5,r5,SVR_P4080@l
236 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
237 lis r3,toreset(enable_cpu_a011_workaround)@ha
238 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
243 oris r3,r3,(L1CSR2_DCWS)@h
248 #ifdef CONFIG_BACKSIDE_L2_CACHE
249 /* skip L2 setup on P2040/P2040E as they have no L2 */
251 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
254 ori r3,r3,SVR_P2040@l
258 /* Enable/invalidate the L2 cache */
260 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
261 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
268 #ifdef CONFIG_SYS_CACHE_STASHING
269 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
274 lis r3,CONFIG_SYS_INIT_L2CSR0@h
275 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
280 andis. r1,r3,L2CSR0_L2E@h
284 /* setup mapping for the spin table, WIMGE=0b00100 */
285 lis r13,toreset(__spin_table_addr)@h
286 ori r13,r13,toreset(__spin_table_addr)@l
289 rlwinm r13,r13,0,0,19
291 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
293 lis r11,(MAS1_VALID|MAS1_IPROT)@h
294 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
296 oris r11,r13,(MAS2_M|MAS2_G)@h
297 ori r11,r13,(MAS2_M|MAS2_G)@l
299 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
300 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
307 * __bootpg_addr has the address of __second_half_boot_page
308 * jump there in AS=1 space with cache enabled
310 lis r13,toreset(__bootpg_addr)@h
311 ori r13,r13,toreset(__bootpg_addr)@l
315 ori r12,r13,MSR_IS|MSR_DS@l
320 * Allocate some space for the SDRAM address of the bootpg.
321 * This variable has to be in the boot page so that it can
322 * be accessed by secondary cores when they come out of reset.
324 .align L1_CACHE_SHIFT
329 .global __spin_table_addr
334 * This variable is set by cpu_init_r() after parsing hwconfig
335 * to enable workaround for erratum NMG_CPU_A011.
337 .align L1_CACHE_SHIFT
338 .global enable_cpu_a011_workaround
339 enable_cpu_a011_workaround:
342 /* Fill in the empty space. The actual reset vector is
343 * the last word of the page */
344 __secondary_start_code_end:
345 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
346 __secondary_reset_vector:
347 b __secondary_start_page
350 /* this is a separated page for the spin table and cacheable boot code */
351 .align L1_CACHE_SHIFT
352 .global __second_half_boot_page
353 __second_half_boot_page:
354 #define EPAPR_MAGIC 0x45504150
355 #define ENTRY_ADDR_UPPER 0
356 #define ENTRY_ADDR_LOWER 4
357 #define ENTRY_R3_UPPER 8
358 #define ENTRY_R3_LOWER 12
359 #define ENTRY_RESV 16
361 #define ENTRY_SIZE 64
364 * r10 has the base address of the spin table.
365 * spin table is defined as
367 * uint64_t entry_addr;
372 * we pad this struct to 64 bytes so each entry is in its own cacheline
377 stw r3,ENTRY_ADDR_UPPER(r10)
378 stw r3,ENTRY_R3_UPPER(r10)
379 stw r4,ENTRY_R3_LOWER(r10)
380 stw r3,ENTRY_RESV(r10)
381 stw r4,ENTRY_PIR(r10)
383 stw r8,ENTRY_ADDR_LOWER(r10)
385 /* spin waiting for addr */
386 3: lwz r4,ENTRY_ADDR_LOWER(r10)
391 /* setup IVORs to match fixed offsets */
392 #include "fixed_ivor.S"
394 /* get the upper bits of the addr */
395 lwz r11,ENTRY_ADDR_UPPER(r10)
397 /* setup branch addr */
400 /* mark the entry as released */
402 stw r8,ENTRY_ADDR_LOWER(r10)
404 /* mask by ~64M to setup our tlb we will jump to */
408 * setup r3, r4, r5, r6, r7, r8, r9
409 * r3 contains the value to put in the r3 register at secondary cpu
410 * entry. The high 32-bits are ignored on 32-bit chip implementations.
411 * 64-bit chip implementations however shall load all 64-bits
413 #ifdef CONFIG_SYS_PPC64
414 ld r3,ENTRY_R3_UPPER(r10)
416 lwz r3,ENTRY_R3_LOWER(r10)
421 lis r7,(64*1024*1024)@h
425 /* load up the pir */
426 lwz r0,ENTRY_PIR(r10)
429 stw r0,ENTRY_PIR(r10)
433 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
434 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
435 * second mapping that maps addr 1:1 for 64M, and then we jump to
438 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
440 lis r10,(MAS1_VALID|MAS1_IPROT)@h
441 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
443 /* WIMGE = 0b00000 for now */
445 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
447 #ifdef CONFIG_ENABLE_36BIT_PHYS
452 /* Now we have another mapping for this page, so we jump to that
462 .space CONFIG_MAX_CPUS*ENTRY_SIZE
464 .space 4096 - (__spin_table_end - __spin_table)