2 * (C) Copyright 2003 Motorola Inc.
3 * Xianghua Xiao (X.Xiao@motorola.com)
4 * Modified based on 8260 for 8560.
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
31 * Minimal serial functions needed to use one of the SCC ports
32 * as serial console interface.
36 #include <asm/cpm_85xx.h>
38 #include <linux/compiler.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 #if defined(CONFIG_CONS_ON_SCC)
44 #if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
47 #define PROFF_SCC PROFF_SCC1
48 #define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
49 CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
50 #define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
51 #define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
52 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
54 #elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
57 #define PROFF_SCC PROFF_SCC2
58 #define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
59 CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
60 #define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
61 #define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
62 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
64 #elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
67 #define PROFF_SCC PROFF_SCC3
68 #define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
69 CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
70 #define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
71 #define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
72 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
74 #elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
77 #define PROFF_SCC PROFF_SCC4
78 #define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
79 CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
80 #define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
81 #define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
82 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
86 #error "console not correctly defined"
90 static int mpc85xx_serial_init(void)
92 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
93 volatile ccsr_cpm_scc_t *sp;
94 volatile scc_uart_t *up;
95 volatile cbd_t *tbdf, *rbdf;
96 volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
99 /* initialize pointers to SCC */
101 sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
102 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
104 /* Disable transmitter/receiver.
106 sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
108 /* put the SCC channel into NMSI (non multiplexd serial interface)
109 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
111 cpm->im_cpm_mux.cmxscr = \
112 (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
114 /* Set up the baud rate generator.
118 /* Allocate space for two buffer descriptors in the DP ram.
119 * damm: allocating space after the two buffers for rx/tx data
122 dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
124 /* Set the physical address of the host memory buffers in
125 * the buffer descriptors.
127 rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
128 rbdf->cbd_bufaddr = (uint) (rbdf+2);
129 rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
131 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
132 tbdf->cbd_sc = BD_SC_WRAP;
134 /* Set up the uart parameters in the parameter ram.
136 up->scc_genscc.scc_rbase = dpaddr;
137 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
138 up->scc_genscc.scc_rfcr = CPMFCR_EB;
139 up->scc_genscc.scc_tfcr = CPMFCR_EB;
140 up->scc_genscc.scc_mrblr = 1;
150 up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
151 up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
152 up->scc_rccm = 0xc0ff;
154 /* Mask all interrupts and remove anything pending.
159 /* Set 8 bit FIFO, 16 bit oversampling and UART mode.
161 sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
163 SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
165 /* Set CTS no flow control, 1 stop bit, 8 bit character length,
166 * normal async UART mode, no parity
168 sp->psmr = SCU_PSMR_CL;
170 /* execute the "Init Rx and Tx params" CP command.
173 while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
176 cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
177 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
179 while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
182 /* Enable transmitter/receiver.
184 sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
189 static void mpc85xx_serial_setbrg(void)
191 #if defined(CONFIG_CONS_USE_EXTC)
192 m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
193 CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
195 m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
199 static void mpc85xx_serial_putc(const char c)
201 volatile scc_uart_t *up;
202 volatile cbd_t *tbdf;
203 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
208 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
209 tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
211 /* Wait for last character to go.
213 while (tbdf->cbd_sc & BD_SC_READY)
216 /* Load the character into the transmit buffer.
218 *(volatile char *)tbdf->cbd_bufaddr = c;
219 tbdf->cbd_datlen = 1;
220 tbdf->cbd_sc |= BD_SC_READY;
223 static void mpc85xx_serial_puts(const char *s)
230 static int mpc85xx_serial_getc(void)
232 volatile cbd_t *rbdf;
233 volatile scc_uart_t *up;
234 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
237 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
238 rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
240 /* Wait for character to show up.
242 while (rbdf->cbd_sc & BD_SC_EMPTY)
245 /* Grab the char and clear the buffer again.
247 c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
248 rbdf->cbd_sc |= BD_SC_EMPTY;
253 static int mpc85xx_serial_tstc(void)
255 volatile cbd_t *rbdf;
256 volatile scc_uart_t *up;
257 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
259 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
260 rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
262 return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
265 static struct serial_device mpc85xx_serial_drv = {
266 .name = "mpc85xx_serial",
267 .start = mpc85xx_serial_init,
269 .setbrg = mpc85xx_serial_setbrg,
270 .putc = mpc85xx_serial_putc,
271 .puts = mpc85xx_serial_puts,
272 .getc = mpc85xx_serial_getc,
273 .tstc = mpc85xx_serial_tstc,
276 void mpc85xx_serial_initialize(void)
278 serial_register(&mpc85xx_serial_drv);
281 __weak struct serial_device *default_serial_console(void)
283 return &mpc85xx_serial_drv;
285 #endif /* CONFIG_CONS_ON_SCC */